A Temperature-Aware Design Methodology for Die-Level Thermal Analysis

1. A Temperature-Aware Design Methodologyfor Die-Level Thermal Analysis Nanda Gopal Gradient Design Automation

2. Outline • Introduction • Thermal Effects on Circuit Performance • FireBolt™ Thermal Analysis Engine • Temperature-Aware Design Methodology • Bridging the Thermal Modeling Gap • Conclusion

3. The Thermal Modeling Gap • Chip assembly is too often a one-way process • Thermal models of the die and package are developed with scarce knowledge of each other • There is a clear gap in the thermal modeling flow • The increasing dominance of temperature as a performance limiting factor requires this gap be bridged

4. Technology Impacts on Chip Behavior • Process trends: • Design trends:

5. Temperature y x Die Temperature is Not Uniform/Constant • On-chip temperature can vary by as much as 500C • Spatial temperature distribution will never attain a uniform, constant value as long as the power distribution varies

6. Design Challenges at Nanometer Processes Power Voltage Drop 90nm 65nm Temperature Electromigration Signal Integrity 130nm Timing Closure 180nm

7. Thermal Impact on Power • Leakage power is seen as dominant at 90nm and below • Device leakage is exponentially dependent on temperature

8. 5% change in Vdd increases cell delay by >11% Thermal Effects on Timing • Cell performance is impacted by voltage drop & temperature • Clock skews are extremely sensitive to on-chip variations • “Delay inversion” effects are being observed at 65nm

9. Q ( ) k.(Tref + T(Jrms)) MTTF = A . Jav-n . e Thermal Impact on Reliability • Black’s equation is used to calculate Mean Time To Failure • Exponential dependence of MTTF on temperature can drastically reduce product lifetimes • 50-75 years @ 60oC  1000-1500 hrs @ 90oC Self heating not considered today

10. Location of thermal diode Peak temperature Current Design Methodology • Lack of predictive and deterministic temperature data • Analysis tools run with inaccurate thermal assumptions • Temperature incorrectly deduced from power • Undetected potential failures • Costly guard-bands and over-design • Poor product reliability • Thermal management systems inadequate • Incorrect placement of temperature sensing diodes • Self-heat in metallization ignored

11. Design layout Power profile Thermal layers Package model Temperature vs leakage power table Annotate initial source power Construct 3D thermal model Update power(T) Solve for 3D temperature End Cell temps Wire temps Final powers FireBolt Thermal Analysis Engine Begin thermal analysis EM analysis Silicon verified Timing analysis IR drop analysis

12. FireBolt Technology • Innovative, high capacity, adaptive algorithms • Incorporation of package and boundary conditions • Bond wire/bumps, molding compounds, epoxies, etc. • True 3D modeling and analysis • Power sources on all layers (devices, wires, vias) • Mixed-level analysis (block  device) • Detailed temperature for all design objects on all layers • Comprehensive data visualization • Temperature, power, power density, heat flux, … • Built on the OpenAccess data model for easy integration

13. FireBolt Data Visualization Power Temperature Thermal Contours Thermal Surface 3D Thermal Isotherms

14. Silicon Verification

15. lib LEF DEF SDC Layers Package layout power Run power analysis SPEF Run timing analysis Thermal repair Run final optimizations Run final route Thermally-Aware Design Flow Build physical prototype FireBolt 3D thermal analysis Thermal delay calculator Run rail analysis Performance-driven Design Flow Incr. SDF

16. Package Models • Package models have viewed the die as a point heat source while increasing the resolution of the package itself • Distributed die temperature must now be considered in the package world to improve overall accuracy

17. Packaging Design Bridging the Thermal Model Gap • Accuracy of package thermal prediction can be improved by coupling 3D package simulation with FireBolt • Allows inclusion of complex cooling mechanisms • Provides a bridge between package and design worlds Die thermal profile FireBolt Design Flomerics Layout Package model

18. Iterative Refinement of Thermal Models Package model at horizontal face of die FireBolt Flomerics Thermal profile at horizontal face of die

19. Effect of Die Temperature on Air Flow Air flow

20. Conclusion • Chip-level thermal analysis is essential for designs <90nm • Thermal analysis must include the effects of the package • On-chip temperature variation affects circuit and package design • FireBolt is the first commercial EDA tool to combine data from process/package/circuit design to compute 3D chip temperature • Tool architecture and interface modules allow for seamless interaction with other tools and capabilities • Current EDA tools and flows must incorporate thermal information as early as possible to avoid temperature-induced design issues