A New ECO Technology foR Functional Changes and Removing Timing Violations

1. A New ECO Technology foR Functional Changes andRemoving Timing Violations Jui-Hung Hung , Yao-Kai Yeh,Yung-Sheng Tseng and Tsai-Ming Hsieh Dept. of Information and Computer Engineering Chung Yuan Christian University

2. Outline • Introduction • Problem Formulation • Algorithm • Experimental Results • Conclusions

3. Outline • Introduction • Problem Formulation • Algorithm • Experimental Results • Conclusions

4. Introduction • The cost of remaking a complete photomask is very expensive, such that spare cells rewiring is a convenient way to repair the problems of functional change or timing violation. • Engineering Change Order (ECO), is an effective technique for fixing circuit functionality and timing problems after the placement stage.

5. Introduction(cont.) • Spare cells are pre-injected after the placement stage and not connect to other cells, therefore we have to modify the netlist information and replace the original standard cell by spare cells.

6. Introduction(cont.) • Assuming that we have to use spare cells to implement a function NAND2 whose two input nets and one output net are denoted by NET1, NET2, NET3

7. Introduction(cont.)

8. Introduction(cont.) • There are two main research directions • ECO for functional changes • ECO for timing optimizations • We can assume the ECO problem as resource allocation problem and competition among timing and functional ECO.

9. Outline • Introduction • Problem Formulation • Algorithm • Experimental Results • Conclusions

10. Problem Formulation(cont.) • Given: • original circuit(netlist and cell placement) • a set of spare cells • a cell library • a set of timing constraints • a set of functional changes. • Our approach is to complete the functional changes by the spare cells rewiring and with the goal of minimum total wiring cost.

11. Problem Formulation • Wiring cost • Sum of the half perimeter of the minimum bounding box (HPBB) of each net. • cost(i) = HPBB(i) = xspan(i)+ yspan(i)

12. Outline • Introduction • Problem Formulation • Algorithm • Experimental Results • Conclusions

13. Algorithm

14. Algorithm(cont.) • Technology Mapping Table Generation • Spare Cell Selection • Matching • Timing Analysis • Buffer Insertion and Gate Sizing

15. Algorithm(cont.) • Technology Mapping Table Generation • We transform the functional change to Boolean expression. • NOR • NAND • DeMorgan’s Theorems • Constant insertion[1]

16. Technology Mapping Table Generation

17. Spare Cell Selection • In spare cell selection, we regard this problem as a question of resource allocation, with timing consideration to choose spare cell combinations with smaller timing influence.

18. Spare Cell Cost Estimation • Using single spare cell • : a set of nets induced by an ECO function which contains input and output nets. • : a spare cell. • :The estimation of wirelength from the spare cell S to the bounding box formed by the e.

19. Spare Cell Cost Estimation(cont.) • Using multiple spare cell

22. Matching • When different ECO functions require the same spare cell, we need to reallocate resources until the requirement is satisfied. • We can define the “spare cell selection for functional change” problem into a resource allocation and competition among timing and functional ECO.

23. Matching(cont.) • Use Hungarian Algorithm to find the better match which with minimum wiring cost in a bipartite graph.

24. Timing Analysis • Apply Synopsys’s Liberty library to simulate the circuit timing. • By the two indexes of input transition time and downstream capacitance, we can calculate the gate delay time and output transition time by lookup tables.

25. Timing Analysis(con’t) • The downstream capacitance calculation is defined as: Downstream components capacitance plus Downstream wire capacitance • Downstream components capacitance • Total input pin capacitance of fan-out gates • Downstream wire capacitance • Sum of the Manhattan distance between current component and the downstream component multiply by the capacitance per wirelength.

26. Buffer insertion and gate sizing • spare cell search range • α : capacitance per unit wirelength • β : a user defined value between 1 to 1.5.

27. Outline • Introduction • Problem Formulation • Algorithm • Experimental Results • Conclusions

28. Experimental Results

29. Experimental Results

30. Outline • Introduction • Problem Formulation • Algorithm • Experimental Results • Conclusions

31. Conclusions • This paper present a new ECO technique for functional changes and timing optimizations simultaneously. • The experimental results show that it not only completes functional changes in a reasonable run time but also fixes most timing violation paths.