digital signal processing basics and ao back ends
Download
Skip this Video
Download Presentation
Digital Signal Processing Basics and AO Back-Ends

Loading in 2 Seconds...

play fullscreen
1 / 54

Digital Signal Processing Basics and AO Back-Ends - PowerPoint PPT Presentation


  • 218 Views
  • Uploaded on

Digital Signal Processing Basics and AO Back-Ends. Luis A. Quintero Digital Section Head Electronics Department Arecibo Observatory. Introduction to Digital Signal Processing. ELECTRICAL VARIABLE Resistance, Capacitance, Voltage, etc. System - World. Quantity. Voltage. Signal

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' Digital Signal Processing Basics and AO Back-Ends' - benjy


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
digital signal processing basics and ao back ends

Digital Signal Processing Basics and AO Back-Ends

Luis A. Quintero

Digital Section Head

Electronics Department

Arecibo Observatory

SDSS7 - DSP and Backends Intro, 12 Jul 2013

slide2

Introduction to Digital Signal Processing

SDSS7 - DSP and Backends Intro, 12 Jul 2013

slide3

ELECTRICAL VARIABLE

Resistance, Capacitance,

Voltage, etc

System - World

Quantity

Voltage

Signal

Conditioning

Transducer

time

time

Continuous Signal Acquisition - Transducers

SDSS7 - DSP and Backends Intro, 12 Jul 2013

slide4

Discrete-time Signal

Amplitude

time

Sampling

Continuous-time Signal (real signal)

Amplitude

time

SDSS7 - DSP and Backends Intro, 12 Jul 2013

signal storage in computers

1V

-1V

- 0.45

+ 0.70

- 0.47

- 0.82

+ 0.30

http://www.iusb.edu/

+ 0.40

- 0.90

Signal Storage in Computers

time

SDSS7 - DSP and Backends Intro, 12 Jul 2013

analog to digital converter quantization

7

6

5

4

3

2

1

0

- 0.45

2

+ 0.70

5

- 0.47

2

- 0.82

1

A/D

+ 0.30

4

+ 0.40

4

- 0.90

6

Analog to Digital Converter – Quantization

time

SDSS7 - DSP and Backends Intro, 12 Jul 2013

analog to digital converter quantization1

D/A

Digital-to-Analog

Converter

Analog to Digital Converter – Quantization

time

2

5

2

1

4

4

6

http://www.iusb.edu/

SDSS7 - DSP and Backends Intro, 12 Jul 2013

digital signal processing system
Digital Signal Processing System

Computer

A/D

D/A

Analog-to-Digital

Converter

Digital-to-Analog

Converter

Computer (Digital System)

- Micro Processor

- DSP (MAC)

- Logic Circuit - ASIC

- PAL/CPLD

- FPGA

Data Storage

Data Processing

- Math Operations

- Filters

- Fourier Transform

- Data Format

SDSS7 - DSP and Backends Intro, 12 Jul 2013

sampling rate analog to digital

time

1 Second

time

Sampling Rate – Analog to Digital

Fs = 9 samples/second = 9Hz

Fs = 19 samples/second = 19Hz

Better signal reconstruction

More computer memory / BW and $$

SDSS7 - DSP and Backends Intro, 12 Jul 2013

analog to digital converter clock input

clk

Analog to Digital Converter - Clock Input

ANALOG

DIGITAL

A/D

Clock for digital circuit

Stable – jitter

SDSS7 - DSP and Backends Intro, 12 Jul 2013

resolution

time

Resolution

Resolution: 3bits, 23 = 8 combinations

7

Values from 0

to 7

0

Resolution: 4bits, 24 = 16 combinations

15

Values from 0

to 15

time

0

Better signal quantization

More computer memory and $$

SDSS7 - DSP and Backends Intro, 12 Jul 2013

saturation

7

time

0

Saturation
  • Resolution: 3bits, 23 = 8 combinations
  • Too much power to the ADC
  • Saturation caused by interference (RFI)

SDSS7 - DSP and Backends Intro, 12 Jul 2013

sampling ft nyquist and aliasing
Sampling – FT, Nyquist and Aliasing

SDSS7 - DSP and Backends Intro, 12 Jul 2013

sampling ft nyquist and aliasing1
Sampling – FT, Nyquist and Aliasing

Fs = 200Hz, Ts = 5ms, Fs/2 = 100Hz

SDSS7 - DSP and Backends Intro, 12 Jul 2013

signal processing adder
Signal Processing – Adder

4bit adder

4

5

=

4

1bit adder

SDSS7 - DSP and Backends Intro, 12 Jul 2013

signal processing multiplier
Signal Processing – Multiplier

4

8

4

  • Multiplication by a Constant – Gain
  • Multiplication by -1, Sign change
  • Multiplication by a function – e.g. sin/cos - up/down conv.
  • Things to consider
  • Bit growing
  • Precision – Approximation Errors

SDSS7 - DSP and Backends Intro, 12 Jul 2013

signal processing functions e g sin cos

DATA

ADDR

n

Phase Increment

Mem - LUT

Signal Processing – Functions, e.g. sin/cos

x[n]

x[n] * sin[n]

sin[n]

DDS

SDSS7 - DSP and Backends Intro, 12 Jul 2013

signal processing synchronization

clk

latency

Signal Processing – Synchronization

SDSS7 - DSP and Backends Intro, 12 Jul 2013

filtering e g finite impulse response fir
Filtering – e.g. Finite Impulse Response (FIR)

SDSS7 - DSP and Backends Intro, 12 Jul 2013

auto correlation
Auto Correlation

SDSS7 - DSP and Backends Intro, 12 Jul 2013

discrete fourier transform dft
Discrete Fourier Transform - DFT

X[k] =FNx[n]

FFT – Fast Fourier Transform, optimized DFT (butterflies)

SDSS7 - DSP and Backends Intro, 12 Jul 2013

slide22

Examples with Signals

  • Fourier Transform
  • Saturation
  • Averaging
  • Clock Jitter

SDSS7 - DSP and Backends Intro, 12 Jul 2013

fourier transform one tone
Fourier Transform, one tone

SDSS7 - DSP and Backends Intro, 12 Jul 2013

fourier transform two tones
Fourier Transform, two tones

SDSS7 - DSP and Backends Intro, 12 Jul 2013

fourier transform noise effect
Fourier Transform, noise effect

SDSS7 - DSP and Backends Intro, 12 Jul 2013

fourier transform averaging
Fourier Transform, averaging

SDSS7 - DSP and Backends Intro, 12 Jul 2013

fourier transform longer transf
Fourier Transform, longer transf.

SDSS7 - DSP and Backends Intro, 12 Jul 2013

fourier transform saturation
Fourier Transform, Saturation

SDSS7 - DSP and Backends Intro, 12 Jul 2013

fourier transform clock jitter
Fourier Transform, Clock Jitter

0% Jitter

40% Jitter

SDSS7 - DSP and Backends Intro, 12 Jul 2013

slide30

Applications in Radio Astronomy

SDSS7 - DSP and Backends Intro, 12 Jul 2013

gregorian dome receivers
Gregorian Dome Receivers

Ganesan, R. “Telescope Electronics”, May 2006

SDSS7 - DSP and Backends Intro, 12 Jul 2013

radio frequency signal path
Radio Frequency Signal Path

SDSS7 - DSP and Backends Intro, 12 Jul 2013

signal transport intermediate freq
Signal Transport – Intermediate Freq.

SDSS7 - DSP and Backends Intro, 12 Jul 2013

final stage data acquisition
Final Stage – Data Acquisition

Data Sampling and Storage

SDSS7 - DSP and Backends Intro, 12 Jul 2013

bandpass signals in if
Bandpass Signals in IF

SDSS7 - DSP and Backends Intro, 12 Jul 2013

sampling nyquist zones analog bw
Sampling - Nyquist Zones & Analog BW

SDSS7 - DSP and Backends Intro, 12 Jul 2013

wideband arecibo pulsar processor wapp
Wideband Arecibo Pulsar Processor (WAPP)
  • 4 WAPPs
  • 1 WAPP = 2 IF Channels
  • 2 Correlators
  • 1 Multiplexer
  • 50/100 MHz BW
  • auto / crosscorrelations
  • Step attenuators
  • Technical issues:
  • Difficult to troubleshoot
  • Obsolete parts

SDSS7 - DSP and Backends Intro, 12 Jul 2013

wideband arecibo pulsar processor wapp1
Wideband Arecibo Pulsar Processor (WAPP)

SDSS7 - DSP and Backends Intro, 12 Jul 2013

wapp correlators 1995
WAPP Correlators (~1995)

High Performance CMOS Correlator Chip (ASIC)

  • 16 Chips per board
  • Autocorrelation / Crosscorrelation
  • 1024 Lags / chip
  • 100MSPS each
  • “Low Power”
  • TTL compatible

http://www.naic.edu/~astro/general_info/correlator/cmos.html

SDSS7 - DSP and Backends Intro, 12 Jul 2013

complex sampling
Complex Sampling

SDSS7 - DSP and Backends Intro, 12 Jul 2013

arecibo l band feed array
Arecibo L-band Feed Array
  • 7 Receivers
  • Dual Polarization
  • 14 analog signals
  • 1225 – 1525MHz
  • 300MHz BW
  • Designed by Germán Cortés Medellín (Cornell)

Ganesan, R. “Telescope Electronics”,

May 2006

SDSS7 - DSP and Backends Intro, 12 Jul 2013

complex sampling example alfa
Complex Sampling Example: ALFA

1225

1525

SDSS7 - DSP and Backends Intro, 12 Jul 2013

mock spectrometer pdev 2007
Mock Spectrometer / PDEV (~2007)
  • Designed and developed by Jeff Mock
  • 8 x AD9430, 12bits ADCs
  • 2 x Xilinx Virtex II Pro FPGA
  • 2 QDR Mem, 2M x 36
  • 1x PowerPC Processor
  • Flash & SRAM mems
  • 2 x GbE, 2 x RS232
  • 5 x SMA (clk, PPS, etc)
  • LCD 128x64 pixels

Digitizers

Digital Board

SDSS7 - DSP and Backends Intro, 12 Jul 2013

pdev architecture
PDEV – Architecture

QDR

2Mx36

Flash /

SRAM

PCIe x8

MGT

ADC

GX

2VP70

ADC

ADC

ADC

2 x GbE

PPC

440GX

2 x RS232

ADC

ADC

GX

2VP70

ADC

ADC

4 x SMA

PCIe x8

MGT

QDR

2Mx36

SDSS7 - DSP and Backends Intro, 12 Jul 2013

pdev mock spectrometer
PDEV – Mock Spectrometer

TEST SIGNAL

CW, Noise,

CW + Noise

12

ADC0

12

ADC0

SWITCH

PROC. INT.

PACKETIZE

STOKES

ACCUMULATOR

GAIN/OFFSET

PFB/FFT 16-8k

DDC (DDS, LPF)

12

ADC0

12

ADC0

CONFIGURATION REGISTERS

SDSS7 - DSP and Backends Intro, 12 Jul 2013

ealfa palfa backend
EALFA / PALFA Backend

14 PDEVs*

7 for 7 ALFA pixels (primary)

7 for 7 ALFA pixels (commensal)

14 File servers (4TB)

We own in total 24 PDEVs

DDC (DDS, Mixer, DLPF)

PFB (up to 8192 channels)

Stokes parameters

Accumulation, Packing

* http://www.naic.edu/~phil/talks/vc09/tel_Perf_datatking_09.ppt

SDSS7 - DSP and Backends Intro, 12 Jul 2013

galfa spectrometer galspect 2004
GALFA Spectrometer / GALSPECT (~2004)
  • Backend for the
  • Arecibo L-band Feed Array (ALFA) multibeam receiver
  • 7 beams, dual polarization
  • Outputs*:
  • Narrowband: 8192channels,
  • 7MHz BW
  • Wideband: 512 channels,
  • 100MHz BW

SDSS7 - DSP and Backends Intro, 12 Jul 2013

pr ultimate pulsar processing instrument puppi
PR Ultimate Pulsar Processing Instrument ( PUPPI)
  • 100/200/400/800MHz BW
  • Polyphase Filter Bank
  • Dual Pol. 8 bit ADC
  • Full Stokes
  • 200MB per second recording (10GbE)
  • 0-15.5dB Level Control
  • PSRFITS data format
  • 1xBee2 + 2xiBOB

SDSS7 - DSP and Backends Intro, 12 Jul 2013

recording systems mark iv 5a 5c rdbe
Recording Systems – Mark IV / 5A / 5C / RDBE
  • Mark IV + Mark 5A: 1Gbps (125MB every second)
  • RDBE + Mark5C: 4Gbps (500MB every second)
  • eVLBI, AO-UPR-Centenial link: 155Mbps all time512Mbps 24h-6h

SDSS7 - DSP and Backends Intro, 12 Jul 2013

roach radar backend rrb
Roach Radar Backend – RRB
  • Complex Baseband - Digital Down Converter (DDC)
  • 50MHz bandwidth max.
  • 2 x IF channels (polA/polB)
  • Bit selection, 8/4bits
  • 1.6Gbps max. data rate
  • Doppler correction
  • Programmable digital filter
  • Hardware (three systems):ROACH – Signal Proc.katADC – [email protected] Server, dual 10GbE
  • Fixed parameters: Summer 2012

SDSS7 - DSP and Backends Intro, 12 Jul 2013

slide51

Analog v.s. Digital

SDSS7 - DSP and Backends Intro, 12 Jul 2013

down conversion
Down Conversion

SDSS7 - DSP and Backends Intro, 12 Jul 2013

digital down conversion
Digital Down Conversion

SDSS7 - DSP and Backends Intro, 12 Jul 2013

questions
Questions?

SDSS7 - DSP and Backends Intro, 12 Jul 2013

ad