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Chapter 5 Register Transfer Languages. Micro-operations RTL RTL specifications Realizing RTL specifications VHDL. Chapter Outline. Specify data transfer Do not specify conditions under which transfers occur Do not specify hardware implementation. Micro-operations. Example: X  Y. X.

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Chapter 5 Register Transfer Languages

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Chapter 5Register Transfer Languages


Micro-operations

RTL

RTL specifications

Realizing RTL specifications

VHDL

Chapter Outline


Specify data transfer

Do not specify conditions under which transfers occur

Do not specify hardware implementation

Micro-operations


Example: X  Y

X


Specify micro-operations and when they occur

Format:conditions: micro-operations

Register Transfer Language


Example: α: X  Y

X


α: X  Y, Y  Z

Simultaneous Data Transfers

Q

D


α: X  Y, X  Z

Invalid Simultaneous Transfers


α: X  0

β: X  1

Loading Constant Values into Registers


Making Transfers Mutually Exclusive


α: X  Y

Multi-bit Data Transfers


Bit and Bit-range Transfers


Arithmetic and Logical Micro-operations


Shift Micro-operations


Specifying Digital Components: D Flip-Flop


Specifying Digital Components: JK Flip-Flop


Specifying Digital Components: Left Shift Register


Specifying Simple Systems


System Implementation – Data Paths


System Implementation – Data Paths and Control


System Implementation Using a Bus and 3-State Buffers


System Implementation Using a Bus and a Multiplexer

n o j


Counts up when U = 1

Count sequence: 000 001  010  011  100  101  000 …

V is 3-bit output = count value

C is 1-bit output = 1 when V = 000

Modulo 6 Counter


Modulo 6 Counter State Table

1 1 1

1 1 1


Modulo 6 Counter State Diagram


Modulo 6 Counter RTL Specification


Modulo 6 Counter System Implementation


Modulo 6 Counter Another System Implementation


C = 1 when car is at toll booth

I[1..0] indicates coin input

Outputs R, G, A:

Car in toll booth, toll not fully paid: R = 1

Toll paid: G = 1

Car left without paying full toll: R = 1, A = 1

Toll Booth Controller


Toll Booth Controller States


Toll Booth Controller State Table


Toll Booth Controller State Diagram


Toll Booth Controller State Assignments


Converting State Transitions to RTL Code


Converting State Transitions to RTL Code


Toll Booth Controller RTL Specification (excluding outputs)


Toll Booth Controller RTL Specification (outputs)


Formal syntax – portable

Platform independent

Design for PLDs, ASICs, or custom chips

Simulate designs

Different levels of abstraction

VHDL – VHSIC Hardware Description Language


Library section

Entity section

Architecture section

VHDL Design Structure


library IEEE;

use IEEE.std_logic_1164.all;

VHDL Library Section


VHDL Entity Section


VHDL Architecture Section


Modulo 6 counter

Designed as a state machine

VHDL – High Level of Abstraction


Modulo 6 Counter – Library and Entity Sections


Modulo 6 Counter – One State


Architecture Section – State Generation


Architecture Section – State Generation (continued)


Architecture Section – State Transition


VHDL – Low Level of Abstraction


Components

Timing

Simulation

VHDL – Advanced Capabilities


Micro-operations

RTL

RTL specifications

Realizing RTL specifications

VHDL

Summary


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