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# Chapter 5 Register Transfer Languages - PowerPoint PPT Presentation

Chapter 5 Register Transfer Languages. Micro-operations RTL RTL specifications Realizing RTL specifications VHDL. Chapter Outline. Specify data transfer Do not specify conditions under which transfers occur Do not specify hardware implementation. Micro-operations. Example: X  Y. X.

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Chapter 5 Register Transfer Languages

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## Chapter 5Register Transfer Languages

Micro-operations

RTL

RTL specifications

Realizing RTL specifications

VHDL

### Chapter Outline

Specify data transfer

Do not specify conditions under which transfers occur

Do not specify hardware implementation

### Example: X  Y

X

Specify micro-operations and when they occur

Format:conditions: micro-operations

X

α: X  Y, Y  Z

Q

D

α: X  Y, X  Z

α: X  0

β: X  1

α: X  Y

### System Implementation Using a Bus and a Multiplexer

n o j

Counts up when U = 1

Count sequence: 000 001  010  011  100  101  000 …

V is 3-bit output = count value

C is 1-bit output = 1 when V = 000

1 1 1

1 1 1

### Modulo 6 Counter Another System Implementation

C = 1 when car is at toll booth

I[1..0] indicates coin input

Outputs R, G, A:

Car in toll booth, toll not fully paid: R = 1

Toll paid: G = 1

Car left without paying full toll: R = 1, A = 1

### Toll Booth Controller RTL Specification (outputs)

Formal syntax – portable

Platform independent

Design for PLDs, ASICs, or custom chips

Simulate designs

Different levels of abstraction

### VHDL – VHSIC Hardware Description Language

Library section

Entity section

Architecture section

### VHDL Design Structure

library IEEE;

use IEEE.std_logic_1164.all;

### VHDL Architecture Section

Modulo 6 counter

Designed as a state machine

### Architecture Section – State Generation

Architecture Section – State Generation (continued)

Components

Timing

Simulation