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Chapter 5 Register Transfer Languages. Micro-operations RTL RTL specifications Realizing RTL specifications VHDL. Chapter Outline. Specify data transfer Do not specify conditions under which transfers occur Do not specify hardware implementation. Micro-operations. Example: X  Y. X.

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Chapter 5 register transfer languages

Chapter 5Register Transfer Languages


Chapter outline

Micro-operations

RTL

RTL specifications

Realizing RTL specifications

VHDL

Chapter Outline


Micro operations

Specify data transfer

Do not specify conditions under which transfers occur

Do not specify hardware implementation

Micro-operations


Example x y
Example: X  Y

X


Register transfer language

Specify micro-operations and when they occur

Format: conditions: micro-operations

Register Transfer Language


Example x y1
Example: α: X  Y

X


Simultaneous data transfers

α: X  Y, Y  Z

Simultaneous Data Transfers

Q

D


Invalid simultaneous transfers

α: X  Y, X  Z

Invalid Simultaneous Transfers


Loading constant values into registers

α: X  0

β: X  1

Loading Constant Values into Registers



Multi bit data transfers

α: X  Y

Multi-bit Data Transfers













Modulo 6 counter

Counts up when U = 1

Count sequence: 000 001  010  011  100  101  000 …

V is 3-bit output = count value

C is 1-bit output = 1 when V = 000

Modulo 6 Counter


Modulo 6 counter state table
Modulo 6 Counter State Table

1 1 1

1 1 1


Modulo 6 counter state diagram
Modulo 6 Counter State Diagram


Modulo 6 counter rtl specification
Modulo 6 Counter RTL Specification


Modulo 6 counter system implementation
Modulo 6 Counter System Implementation


Modulo 6 counter another system implementation
Modulo 6 Counter Another System Implementation


Toll booth controller

C = 1 when car is at toll booth

I[1..0] indicates coin input

Outputs R, G, A:

Car in toll booth, toll not fully paid: R = 1

Toll paid: G = 1

Car left without paying full toll: R = 1, A = 1

Toll Booth Controller










Vhdl vhsic hardware description language

Formal syntax – portable

Platform independent

Design for PLDs, ASICs, or custom chips

Simulate designs

Different levels of abstraction

VHDL – VHSIC Hardware Description Language


Vhdl design structure

Library section

Entity section

Architecture section

VHDL Design Structure


Vhdl library section

library IEEE;

use IEEE.std_logic_1164.all;

VHDL Library Section




Vhdl high level of abstraction

Modulo 6 counter

Designed as a state machine

VHDL – High Level of Abstraction








Vhdl advanced capabilities

Components

Timing

Simulation

VHDL – Advanced Capabilities


Summary

Micro-operations

RTL

RTL specifications

Realizing RTL specifications

VHDL

Summary


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