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# Chapter 5 Register Transfer Languages - PowerPoint PPT Presentation

Chapter 5 Register Transfer Languages. Micro-operations RTL RTL specifications Realizing RTL specifications VHDL. Chapter Outline. Specify data transfer Do not specify conditions under which transfers occur Do not specify hardware implementation. Micro-operations. Example: X  Y. X.

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### Chapter 5Register Transfer Languages

RTL

RTL specifications

Realizing RTL specifications

VHDL

Chapter Outline

Do not specify conditions under which transfers occur

Do not specify hardware implementation

Micro-operations

Example: X  Y

X

Format: conditions: micro-operations

Register Transfer Language

Example: α: X  Y

X

α: X  Y, Y  Z

Simultaneous Data Transfers

Q

D

α: X  Y, X  Z

Invalid Simultaneous Transfers

α: X  0

β: X  1

α: X  Y

Multi-bit Data Transfers

Count sequence: 000 001  010  011  100  101  000 …

V is 3-bit output = count value

C is 1-bit output = 1 when V = 000

Modulo 6 Counter

Modulo 6 Counter State Table

1 1 1

1 1 1

Modulo 6 Counter State Diagram

Modulo 6 Counter RTL Specification

Modulo 6 Counter System Implementation

Modulo 6 Counter Another System Implementation

I[1..0] indicates coin input

Outputs R, G, A:

Car in toll booth, toll not fully paid: R = 1

Toll paid: G = 1

Car left without paying full toll: R = 1, A = 1

Toll Booth Controller

Platform independent

Design for PLDs, ASICs, or custom chips

Simulate designs

Different levels of abstraction

VHDL – VHSIC Hardware Description Language

Entity section

Architecture section

VHDL Design Structure

use IEEE.std_logic_1164.all;

VHDL Library Section

Designed as a state machine

VHDL – High Level of Abstraction

Timing

Simulation