Various power gating techniques to reduce power dissipation in various macros of microprocessors
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Various Power Gating techniques to reduce power dissipation in various macros of microprocessors. By Sai Raghunath T. Goal:. Reduction of standby power dissipation from execution unit and memory unit using power gating techniques Specifications and tools used:

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Various Power Gating techniques to reduce power dissipation in various macros of microprocessors

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Various power gating techniques to reduce power dissipation in various macros of microprocessors

Various Power Gating techniques to reduce power dissipation in various macros of microprocessors

By

Sai Raghunath T


Various power gating techniques to reduce power dissipation in various macros of microprocessors

Goal:

  • Reduction of standby power dissipation from execution unit and memory unit using power gating techniques

    Specifications and tools used:

  • Two 32-bit ALUs are implemented using Transmission gates by static design logic and alternating static and dynamic logic

  • SRAM memory with 16Rx8W is implemented. Each word is 16 bits in length.

  • TSMC 0.24um technology files are used in the design of ALUs and SRAM.

  • Design is carried out with Cadence EDA tool.


Proposed work

Proposed work

  • Implementation of 32 bit ALU and use various power gating techniques (listed below) to reduce the standby power leakage.

  • Input vector control with and without body biasing.

  • MTCMOS with selective MT technique

  • SRAM- 16rows x (16*8) columns

  • Lone nMOS data retention circuitry

  • Lone pMOS data retention circuitry


Work carried out

Work carried out

  • Implementation of a 32-bit ALU using Transmission gates and Carry bypass adder

  • Implementation of a 32-bit ALU using Transmission gates and Han Carlson adder

    (both with and without input vector control body biasing)

  • Implementation of SRAM bank of 16R X 8W in 250nm technology with data retention circuitry and power gating. Each word is 16 bits in length.


Block diagram of 32 bit alu

Block diagram of 32-bit ALU

32x9 i/ps32x9 i/ps

9x1 Mux

9x1 Mux

31

0

31

0

Shifter

2x1 Mux

31

0

31

0

Adder

Cout

0

31


Power gating circuitry used

Power gating circuitry used


Basic sram cell

BLB

BL

WL

WL

pmos-pu

pmos-pu

nmos

nmos-pg

nmos-pd

nmos-pd

Wn of nmos-pd :1.08um

Wn of nmos-pg :720nm

Wp of pmos-pu: 360nm

Basic SRAM cell


Deviations from the proposed work

Deviations from the proposed work

  • MTCMOS with selective MT technique is not implemented as students are not permitted to change the threshold voltage of the transistors of a model file in ASU.

  • After a brief research on data retention circuitry and power gating for SRAMs, nmos power gating circuitry and pmos data retention circuitry is implemented.


Data retention and power gatin circuitry used

Data retention and power gatin circuitry used

SRAM bank


Results

Results

  • 32 bit ALU with Transmission gates and Carry bypass adder:

    Standby leakage power without power gating=13.25uW

    Standby leakage power with power gating=72.25pW

  • 32 bit ALU with Transmission gates and Han Carlson adder:

    Standby leakage power without power gating=10.78uW

    Standby leakage power with power gating= 28.2pW

  • SRAM bank (16Rx8W)

    Standby leakage power without nmos power gating circuitry and pmos data retention circuitry=30.7pW

    Standby leakage power with nmos power gating circuitry and pmos data retention circuitry = 13.51pW


References

References

[1]. Zhigang Hu; Buyuktosunoglu, A.; Srinivasan, V.; Zyuban, V.; Jacobson, H.; Bose, P, “Microarchitectural Techniques for Power Gating of Execution Units” in ISPLED, 2004 Page(s):32 - 37

[2]. Hailin Jiang; Marek-Sadowska, M.; Nassif, S.R,“Benefits and costs of power-gating technique”in ICCD,2005 Page(s):559 – 566

[3]. Chung-Hsien Hua and Wei Hwang, "A Power Gating Structure with Concurrent Data Retention and Intermediate Modes in 100nm CMOS Technology" in 15th VLSI Design/CAD Symposium, 2004

[4]. Suhwan Kim; Kosonocky, S.V.; Knebel, D.R.; Stawiasz, K., “Experimental measurement of a novel power gating structure with intermediate power saving mode” in ISPLED, 2004 Page(s):20 - 25


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