1 / 39

iTOP readout firmware development

Not shown: Joshua Sopher (firmware) Lili Zhang (DSP coding). iTOP readout firmware development. K. Nishimura and G. Varner 25-MAR-2011 lDAQ meeting. Overview. Status of various components Immediate deadline  cosmic test in Japan Essential gate prior to CERN beam test

benita
Download Presentation

iTOP readout firmware development

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Not shown: Joshua Sopher (firmware) Lili Zhang (DSP coding) iTOP readout firmware development K. Nishimura and G. Varner 25-MAR-2011 lDAQ meeting

  2. Overview • Status of various components • Immediate deadline  cosmic test in Japan • Essential gate prior to CERN beam test • Today focus on this first deadlines • ASICs: BLAB3A or IRS2+amps • Progress on the 128-channel readout module • Firmware/software development issues • Kurtis will discuss schedule

  3. 64 DAQ fiber transceivers 32 FINESSE 8 COPPER iTOP Readout Overview 8k channels 1k 8-channel waveform ASICs 64 SRM Precision timing requires 64 channels high-precision clock distribution (<~ 10ps) Approximately 30m runs

  4. Major milestone:1/16 system test Third generation waveform sampling ASIC Clock jitter cleaners

  5. A very crowded location! 8k vs. 14k (CDC channels) << 10% of space!

  6. First prototype iteration results Does not work

  7. Proposed modular solution

  8. Top view of new electronics showing the positions of the fiber transceivers and overall width 424.2mm 312.2mm 200.2mm 88.2mm 30mm 475.2mm

  9. Top view of new electronics showing the positions of the fiber transceivers and overall width_030111. Suzuki-san and Kohriki-san would like to see the fibers clustered into two ingress/egress positions. 424.2mm 312.2mm 200.2mm 88.2mm 30mm 475.2mm

  10. Such a change NOT a viable option • Would require 2 completely different designs • Firmware would have to be different! • Timing would be different, different systematic effects, cannot interchange parts… • Marc will discuss proposed reconfiguration • Helps with module seating/cooling • Other cable routing, cooling more plausible • Rest of talk about components

  11. Proposed modular solution

  12. BLAB3 Specifications • Time alignment critical • Synchronize sampling to accelerator RF clock • >5us a must for trigger, since single photon rates high • Needs Gain!

  13. 5.82mm BLAB3/IRS (amp/no-amp) 7.62mm 8x RF inputs (die upside down) 32k storage cells per channel (512 groups of 64)

  14. Sampling: 128 (2x 64 separate transfer lanes BLAB3/IRS Single Channel Recording in one set 64, transferring other (“ping-pong”) • Storage: 64 x 512 (512 = 8 * 64) • Wilkinson (32x2): 64 conv/channel

  15. Sampling speed

  16. IRS2 DC Linearity Calibration ARA Digitizer - 12-MAR-2011

  17. IRS2 Noise Measurement <1mV 10-15%

  18. Measurement via RF sine Analog BW ~1GHz

  19. BLAB3A testing (carrier board) 23mm x 50mm Plan to submit soon BLAB3A

  20. Proposed modular solution

  21. SCROD feasible?(mid-October)

  22. brainstorming the mechanical mockup(mid-November)

  23. Might work mechanically, if can really fit components…

  24. mechanical mockup(mid-November)

  25. brainstorming SCROD

  26. SCROD block diagram

  27. status of SCROD layout on Dec 23rd

  28. SCROD Fabricated • Rest of board stack needed: • Firmware!!

  29. Proposed modular solution

  30. Can work problem from other direction: • 2.4Gbps (on 3Gbaud link) • At 30kHz L2 (100ns window, 0.3% RealTime) • 80kbits/event at 512 bits/hit ~= 150 hits/link • ~600 hits/event/iTOP counter • Expect ~4 background p.e./event • Maintain > 10x link margin Data link margin (re-visited)

  31. cPCI_DSP BLAB3A Or IRS2+ amps Beam test: a 1/16 system test Third generation waveform sampling ASIC Not needed Clock jitter cleaners SCROD-based Modules Nakao-san’s version?

  32. Summary/Open issues • Much firmware work needed • Help from PNNL; write system documentation • Hardware – confirm items previous slide • Complete BLAB3A carrier, routing boards • Interface board done, submit 3x designs soon • Confirm performance of integrated module, including with MCP-PMTs • Development manpower resource limited (next talk)

  33. Back-up slides

  34. Photo-detector: Hamamatsu SL-10 • Micro-channel Plate: • Operates in 1.5T B-field • <50ps single photon timing • Multi-pixel (4x4 anode pads) • Enhanced Lifetime (Al protection layer) • Interesting mechanical challenges (PMT case at HV) Approximately 1” x 1”

  35. BLAB3 status and schedule * = not for Belle2, but will learn from design

  36. SL-10 Timing Performance Hawai’i Nagoya σ ~ 38.37 • Nagoya = constant fraction discriminator + CAMAC ADC/TDC • Hawai’i = waveform sampling + feature extraction

  37. High speed Waveform sampling“oscilloscope on a chip” Comparable performance to best CFD + HPTDC MUCH lower power, no need for huge cable plant! Using full samples reduces the impact of noise Photodetector limited CH1 CH2 6.4 psRMS NIM A602 (2009) 438 • Advanced Detector Research award

  38. Belle2 barrel PID upgrade: iTOP

  39. references and further info • references: • http://b2comp.kek.jp/~twiki/pub/Organization/B2TDR/B2TDR.pdf • http://www.phys.hawaii.edu/~idlab/taskAndSchedule/ICBMS.pdf • latest info: • http://idlab.phys.hawaii.edu/pcb-designs/scrod

More Related