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Out-panel Overview

Out-panel Overview. Crate-based (VME 9U) architecture. 4 crates for entire MUID system: North Horizontal, North Vertical, South Horizontal, South Vertical 1 Front End Module (FEM) per crate communicates with PHENIX Online: Serial Control Timing & Control Data Collector Modules (DCM).

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Out-panel Overview

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  1. Out-panel Overview • Crate-based (VME 9U) architecture. • 4 crates for entire MUID system: • North Horizontal, North Vertical, South Horizontal, South Vertical • 1 Front End Module (FEM) per crate communicates with PHENIX Online: • Serial Control • Timing & Control • Data Collector Modules (DCM)

  2. Out-panel Overview - cont. • 20 96-channel Readout Cards (ROCs) perform analog processing and communicate with LVL1. • 20 Transition Cards (TCs) (1 per ROC) allow input signals to enter from backplane. • Passthrough backplanes on P1 and P2 connect each TC to its ROC. • Modified VME backplane for ROC/FEMcommunication, geographical addressing and power distribution.

  3. ROC : : : ROC FEM Crate 16 6 sets of 16 twisted-pairs from Iarocci tube panels 20 Read Out Cards (ROCs) : 16 GLink to LVL1 (60 MHz) Serial Data and Control lines on backplane 16 6 sets of 16 twisted-pairs from Iarocci tube panels : 16 GLink to LVL1 (60 MHz) Controller Card GLink to DCM (20 MHz) GLink from T&C (40 MHz) Arcnet line

  4. Front of FEM Crate C O N T R O L R O C R O C R O C

  5. Arcnet T&C Glink DCM Glink Trigger Glinks Analog Lemos Digital Lemos FEM Crate Profile P1 Analog Data Electronics cards Transition cards Data From Panels P2 P3 Custom Digital Backplane Power Supply Fans

  6. WR Clk & EN (2) /RD RD Clk & EN (2) LVL1_Acpt BCLK Arcbus (10) FPGA Program (6) ARCnet serial line FEM Block Diagram P3 Backplane Front Panel Strobe, /CAV, /Dav FPGA 16 Data Formatter ROC Data Data (16) FIFO 5 GLink To DCM GLink XMIT FEM Addr /ALE /ROC_DV GLink From T&C Tx Reset, Locked, ED Command Lines (7) LVL1accept BCLK 4xBCLK ENDAT0 UserBit[2:0] ModeBits[7:0] Mode Enable Mode Bits (20) /HALT Mode Control GLink RCV FPGA Program (6) Resets (4) Align bit Address & RD Cntrl (7) Rx Reset, Stat0 Data (16) Arcnet Subsystem 5 Arc Addr/Data Mode CLK Xfer Mode (2) MP_dat (2) Data Formatter Diagnostic FPGA Serial Data (6) Address Decode PLD Geographic Address (6)

  7. FEMs • State machine for ROC/FEM communication: • Builds event header/trailer words. • Cycles through ROCs, copying data into DCM FIFO: • 96 data bits per ROC • Plus 16 bit beam clock counter to identify I/O errors • FPGA implementation, simulated. • State machine for T&C communication (mode control): • FPGA implementation, simulated.

  8. FEMs - cont. • Self-tester to allow complete FEM testing in the absence of full crate of ROCs. • FPGA implementation, schematics finished, simulated. • Address decoder (identical for FEM and all ROCs) uses geographical address to direct serial control and data traffic on digital backplane. • CPLD implementation, simulated. • ORCAD schematics in progress. • Stealing (working!) schematics from PC for ARCnet, T&C and DCM links.

  9. { 16 16 16 P1 96 16 32 32 16 16 16 16 32 16 16 16 { 16 16 16 16 analog data 96 16 16 6 20 Xfer Mode (2) MP_dat (2) Greset /ALE ED Locked Backplane ROC Block Diagram FIFO cntrl 16 Receiver & Threshold Delay & Latch FPGAs (6) and Clock delay chips (12) Data Store FIFOs (3) Five Event FIFO FPGA analog data Data LVL1_Acpt /RD /RD_EN /DV P2 sdin, rdback, slatch, sclk, sdout, sreset Pulser lines BCLK 6 96 Analog Spy Output Analog Muxes (7) 96 28 /HALT Serial String & Pulser Align bit LVL1_Acpt BCLK { Digital Spy Output Board Resets (4) /RD FPGA Prog. Align bit Trigger Format FPGA /DV Trigger Data 6 Data (16) P3 5 6X BCLK Address Decode PLD Mode CLK Trigger GLink (60 MHz) /RD_EN TTL GLink Circuit FEM Device Addr (5) Arcnet Addr/Data (5) Geographic Address (6)

  10. ROCs • 96-channel implementation: • Multiple of input cable size (6x16=96). • Fits into single optical G-link connection to LVL1 (with 6*BMCLK multiplexing). • Minimum #channels that simultaneously allows: • Horizontal/Vertical ROC segregation • Standard (21-slot) VME crates • Only 4 DCMs

  11. ROCs - cont. • Analog processing chain. • Supplemental diagnostics. • Serial control. • All FPGAs schematics in hand and simulated. • ORCAD schematics in progress.

  12. ROCs: Analog Processing Chain - Receiver, Discriminator • Differential Receiver • Prototype panel used amplification of 1 w/ Thresh = 40mV and 50/50 isobutane/CO2. • Amplification of 3 chosen: • Optimize filtering and minimize “popcorn” • As a hedge against possibility of smaller operating gas gain (lower isobutane concentration) • Discriminator • Leading edge seen to be sufficient on prototype. • Range: 12.5 - 500 mV (256 steps). • Selectability every 4 channels.

  13. ROCs: Analog Processing Chain - Variable Delay • Pipeline nature of PHENIX DAQ leads to requirement that all signals arrive within one beam clock cycle (106 ns).

  14. ROCs: Analog Processing Chain - Variable Delay - cont. • Maximum gate width reduced to 90 ns by set/hold requirements. • Further reduced to 80 ns by convolution with transmission time down length of LST. • Failure to match T0 leads to 1% efficiency loss every 3 ns. Inefficiency vs. gate width for different isobutane/CO2 ratios. Measurement is for a 2-pack at one longitudinal location.

  15. ROCs: Analog Processing Chain - Variable Delay - cont.

  16. ROCs: Analog Processing Chain - Variable Delay - cont. • Specification • 50ns dynamic range total (25ns w/i input cable) • 4ns resolution • 1ns precision • Staged implementation • CPLD portion simulated • Full circuit to be tested on 8-channel prototype

  17. ROCs: Analog Processing Chain - Outputs • LVL1 trigger: • 96-bit struck LST pattern. • 6*BMCLK MUX (schematic from H. Skank) into optical G-link connection (1 per ROC on front panel). • DCM: • Bit pattern from every beam crossing is strobed into 64-deep FIFO to cover LVL1 latency. • Data from events from valid LVL1 is strobed into 5-event-deep FIFO. • Data from 5-event FIFO on each ROC is sent to DCM event FIFO on FEM.

  18. ROCs - Supplemental Diagnostics • Pulser • Selectable every four channels. • Allows diagnostics w/o being connected to a detector. • Spy MUXes • Analog MUX samples immediately after the receiver. • Digital MUX samples immediately after the variable delay. • Both allow looks at signals, one channel at a time. • Both are channel-selectable via serial control. • Both outputs drive 50W to front-panel LEMO connectors. • Output Mask • Allows elimination of known bad channels. • Allows arbitrary bit patterns, e.g., to test trigger algorithms.

  19. ROCs - Serial Control • Signal routing via address decoder CPLD identical to that described for the FEM. • Pulser select • MUX selects • Output mask select • Threshold DACs • Variable delay settings • FPGA programming

  20. 8-Channel ROC Prototype • Will test analog processing chain through variable delay. • Will test “final” layout of analog portion of board. • NIM resident, currently being stuffed. • Will be tested on full-scale prototype.

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