Mtest pixel telescope status update
This presentation is the property of its rightful owner.
Sponsored Links
1 / 14

MTest Pixel Telescope – Status Update PowerPoint PPT Presentation


  • 74 Views
  • Uploaded on
  • Presentation posted in: General

MTest Pixel Telescope – Status Update. David Christian January 8, 2008. Detector Status/Plan. Hybrid development complete 11 good hybrids in hand Balance waiting for LANL PO to VTT Delivery Jan – Feb (less schedule risk than before) Module development

Download Presentation

MTest Pixel Telescope – Status Update

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


Mtest pixel telescope status update

MTest Pixel Telescope – Status Update

David Christian

January 8, 2008


Detector status plan

Detector Status/Plan

  • Hybrid development complete

    • 11 good hybrids in hand

    • Balance waiting for LANL PO to VTT

      • Delivery Jan – Feb (less schedule risk than before)

  • Module development

    • 4x HDI prototype received & tested (12 good parts in hand).

    • Production purchase requisition is working its way through the FNAL bureaucracy (Feb delivery expected).


Detector status plan continued

Detector Status/Plan continued

  • Plane/Station development:

    • First prototype plane being tested (one of three pixel modules mounted so far).

    • SLINK pcb prototype has been received, stuffed, & testing has begun (Nevis).

  • Box/Area:

    • Mechanical design to be coordinated with needs of LHCb VELO (1st users) - waiting for MOU to be signed (momentarily).


Plane prototype on cmm

Plane prototype on CMM


1 st module ready to test

1st module ready to test


Daq status plan

DAQ Status/Plan

  • DAQ Hardware/Firmware (Nevis)

    • PCI interface ~90% complete (trigger/timing hooks not written)

    • Router ~70% complete (trigger/timing, implementation of merges, integration of DUT?)

    • SLINK

      • Design complete.

      • Prototype fabricated; tests begun.

      • On the optimistic critical path - hoping to begin testing with a prototype station (or at least a plane) ~ Feb 1.


Software status plan

Software Status/Plan

  • Online software (FNAL, Syracuse, UNM?)

    • Core low level routines exist & have been tested.

    • Need to specify online, including online/offline boundary, write & test code.

      • On the optimistic critical path

  • Offline software (Syracuse, FNAL?, UNM?)

    • Data unpacking

    • Alignment

    • Tracking, integration of DUT

      • On the optimistic critical path

  • This task has lagged. Strategic decisions to be made in the next 2-4 weeks.


Schedule

Schedule

  • Focus on full telescope ASAP. February doesn’t look possible. March?


Mtest telescope

MTest Telescope

  • Constructed using “BTeV pixels”

  • Pixel size = 50m x 400m (600m)

  • Oriented to provide “precision-x” or “precision-y” measurements.


Layout

Layout

  • Aperture ~ 3.5cm x 3.5cm

  • 4 – 6 stations

y

y

Beam

x

x


Nomenclature

Nomenclature

  • Station = 2 planes & an SLINK

  • Plane = 3 modules mounted on a TPG heat spreader

  • Module = hybrid pixel detector glued & wire-bonded to a High Density Interconnect (Kapton flex circuit)

  • Hybrid = pixel sensor bump bonded to 4 FPIX2.1 ASICs


Daq overview

DAQ Overview

ROUTER

SLINK

Trigger/timing signals

Twin-ax

(sATA)

Removable disk

Fiber

PCI Interface

LINUX pc

Trigger/timing signals


Mtest pixel telescope status update

DAQ

  • SLINK communicates with 2x3x4=24 FPIX2.1 chips & with ROUTER.

    • Relays commands & responses

    • Collects data

      • Deserialize (digital phase follower)

      • Time order & construct data blocks w/extended time stamp & chip ID headers

      • Hierarchy of 2-way data merges


Daq continued

DAQ - continued

  • ROUTER communicates with PCI interface & SLINKs and (optionally) DUTs

    • 12 sATA ports, 4 RJ45 ports

    • Relays commands & responses

    • Collects data

      • Hierarchy of 2-way data merges (same logic as SLINK)

  • PCI Interface communicates with ROUTER & pc

    • Relays commands & responses

    • Uses 3 CSRs & 3 ring buffers in the pc main memory (64 MB)


  • Login