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Review: Fan-In ConsiderationsPowerPoint Presentation

Review: Fan-In Considerations

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### EE534VLSI Design SystemSummer 2004 Lecture 12:Chapter 7&9Transmission gate andDynamic logic circuits design approaches

### Ratioed Logic

### Chapter 9 reduce area and delayDynamic logic circuits design

C

B

A

C3

C2

C1

CL

Review: Fan-In ConsiderationsA

B

Distributed RC model

(Elmore delay)

TpHL=0.69[R1C1+(R1+R2)C2+(R1+R2+R3)C3+(R1+R2+R3+R4)CL]

tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)

Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case.

C

D

Review: tp as a Function of Fan-In

quadratic function of fan-in

tp (psec)

tpHL

tp

tpLH

linear function of fan-in

fan-in

- Gates with a fan-in greater than 4 should be avoided.

DD

A

B

A

B

C

D

Review: Influence of Fan-In and Fan-Out on Delay- Fan-out: Number of Gates connected to the output
- in static CMOS, there are two gate capacitances per Fan-out

- Fan-in: Number of independent variables for the logic function, which has a quadratic effect on tp due to:
- resistance increasing
- capacitance increasing

C

D

C3

C2

C1

CL

Fast Complex Gates: Design Technique 1- Transistor sizing
- as long as fan-out capacitance dominates

- Progressive sizing

Distributed RC line

M1 > M2 > M3 > … > MN

(the MOSFET closest to the output should be the smallest)

InN

MN

In3

M3

In2

M2

Can reduce delay by more than 20%; decreasing gains as technology shrinks

In1

M1

Resistance of M1(R1) N times in the delay

Equation. The resistance of M2(R2) appears N-1 times etc.

C2

C1

C1

C2

CL

CL

Review : Fast Complex Gates: Design Technique 2- Input re-ordering
- when not all inputs arrive at the same time

critical path

critical path

01

charged

charged

1

In1

In3

M3

M3

1

1

In2

In2

M2

discharged

M2

charged

1

In3

discharged

In1

charged

M1

M1

01

delay determined by time to discharge CL, C1 and C2

delay determined by time to discharge CL

C

B

A

C3

C2

C1

CL

Review: Sizing and Ordering Effects3

3

3

3

A

4

4

= 100 fF

B

4

5

Progressive sizing in pull-down chain gives up to a 23% improvement.

Input ordering saves 5%

critical path A – 23%

C

4

6

D

4

7

Ratioed logic is an attempt to reduce

The number of transistors required to implant a given logic function, often at the cost of reduced robustness and extra power dissipation

Other logic styles

- Transmission gate logic
- Pass-transistor logic
- NMOS transistors used as switches
- Other variants:
- Complementary pass-transistor logic (CPL)
- Swing-restored pass-transistor logic

Transmission Gate Logic

- NMOS and PMOS connected in parallel
- Allows full rail transition – ratioless logic
- Equivalent resistance relatively constant during transition
- Complementary signals required for gates
- Some gates can be efficiently implemented using transmission gate logic

=

=

Transmission Gates (pass gates)

Use of transistors as switches are called transmission gates because switches can transmit information from one circuit to another.

CMOS Transmission Gate

- A CMOAS transmission gate can be constructed by parallel combination of NMOS and PMOS transistors, with complementary gate signals.
- The main advantage of the CMOS transmission gate compared to NMOS transmission gate is to allow the input signal to be transmitted to the output without the threshold voltage attenuation.

CMOS transmission gate

Drain

Drain

source

Characteristics of a CMOS Transmission gate- Case I:
If =VDD, , VI=VDD, and VO is initially zero.

In NMOS transistor, under above Condition, terminal ‘a’ acts as the drain and terminal ‘b’ acts as the source.

For the PMOS, device terminal ‘c’ acts as the drain and terminal ‘d’ acts as the source. In order to charge the load capacitor, current enters the NMOS drain and the PMOS source. The NMOS gate to source voltage is,

VGSN = - VO = VDD - VO

this implies that VGSN continuously change.

And for PMOS source-to-gate voltage is

VGSP = VI - = VDD – 0 = VDD

This implies that VGSP remains constant.

Charging path

Characteristics of a CMOS Transmission gate (Cont.)

- When VO=VDD-VTN,VGSN=VTN,
the NMOS transmission gate cuts

off and IDN=0.

However, PMOS transistor continue to conduct, because VGSP of the PMOS is a constant

(VGSP=VDD). In PMOS transistor

IDP=0, when VSDP=0, which would be

possible only, if,

VO = VI = 5V

This implies that a logic ‘1’ is transmitted unattenuated through

the CMOS transmission gate in contrast to the NMOS transmission

gate.

NMOS transmission gate

Characteristics of a CMOS Transmission gate (Cont.)

- Case II:
If VI = 0, = VDD, VO=VDD initially.

terminal ‘a’ acts as a source and terminal

‘b’ acts as a drain.

For the PMOS transistor terminal

‘c’ acts as a source and terminal ‘d’ acts as a drain.

In order to discharge the capacitors current enter the NMOS drain and PMOS source. The NMOS gate to source voltage is,

And PMOS source to gate voltage is

When VSGP=VO=|VTP|, PMOS transistor cutoff and iDP=o

However, since VGSN=VDD, the NMOS transistor continue

conducting and capacitor completely discharge to zero.

Finally, VO=0, which is a good logic 0.

discharging path

drain

source

drain

source

Equivalent Resistance Model

- For a rising transition at the output (step input)
- NMOS sat, PMOS sat until output reaches |VTP|
- NMOS sat, PMOS lin until output reaches VDD-VTN
- NMOS off, PMOS lin for the final VDD – VTN to VDD voltage swing

Equivalent Resistance – Region 1

- NMOS sat:
- PMOS sat:

- NMOS sat, PMOS sat until output reaches |VTP| because drain to source voltage is still high

Equivalent Resistance – Region 2

- NMOS sat:
- PMOS lin:

NMOS sat, PMOS lin until output reaches VDD-VTN

Equivalent Resistance – Region 3

- NMOS off:
- PMOS lin:

- NMOS off, PMOS lin for the final VCC – VTN to VCC voltage swing

Equivalent resistance

- Equivalent resistance Req is parallel combinaton of Req,n and Req,p
- Req is relatively constant
- This property of CMOS TG is quite desirable

Delay Optimization

Example: 16 cascade minimum size transmission gates with resistance of 8K

C=3.6fF for low to high transition. The delay is given by

Use of long pass transistors chains causes significant delay degradation

What could be the possible solution to minimize this delay?

Break the chain and insert buffers

The insertion of the buffer inverters reduces the delay by a factor of almost 2

CMOS transmission gate remains in a dynamic condition.

- If VO=VDD, then NMOS substrate to terminal ‘b’ pn junction is reverse biased and capacitor CL can discharge.
- If VO=0, then the PMOS terminal c-to-substrate pn junction is reverse biased and capacitance CL can be charge to a positive voltage.
- This implies that the output high or low of CMOS transmission gate circuit do not remain constant with time (dynamic behavior).

Dynamic CMOS

- Advantages:
- Faster – why?
- Reduced input load
- No switching contention

- Less layout area

- Faster – why?
- Disadvantages:
- Charge leakage
- Charge sharing
- Capacitive coupling
- Cannot be cascaded
- Complicated timing/clocking
- Higher power
- Lower noise margins

clk

NMOS network

clk

Gnd

These issues are discussed in chapter 9

TG Applications: Multiplexer (MUX) circuit

- Case I: When the input S is logic high
Bottom transistor is conducting and output is equal to input B

- Case II: When the input S is logic low
Bottom Tg turn off and top TG turn on and output is equal to input A

A Revised Adder Circuit: applying the design techniques to reduce area and delay

Transmission Gate Full Adder reduce area and delay

Similar delays for sum and carry

Dynamic CMOS reduce area and delay

- In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.
- fan-in of n requires 2n (n N-type + n P-type) devices

- Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.
- requires on n + 2 (n+1 N-type + 1 P-type) transistors

Static vs Dynamic Storage reduce area and delay

- Static storage
- preserve state as long as the power is on
- have positive feedback (regeneration) with an internal connection between the output and the input
- useful when updates are infrequent (clock gating)

- Dynamic storage
- store state on parasitic capacitors
- only hold state for short periods of time (milliseconds)
- require periodic refresh
- usually simpler, so higher speed and lower power

Evolution from static to dynamic logic gate reduce area and delay

Dynamic CMOS reduce area and delay

- Advantages:
- Faster – why?
- Reduced input load
- No switching contention

- Less layout area

- Faster – why?
- Disadvantages:
- Charge leakage
- Charge sharing
- Capacitive coupling
- Cannot be cascaded
- Complicated timing/clocking
- Higher power
- Lower noise margins

clk

NMOS network

clk

Gnd

Clk reduce area and delay

Mp

((AB)+C)

Out

CL

A

C

B

Clk

Me

Dynamic Gateoff

Clk

Mp

on

1

Out

In1

In2

PDN

In3

Clk

Me

off

on

Two phase operation

Precharge (Clk = 0)

Evaluate (Clk = 1)

Conditions on Output reduce area and delay

- Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.
- Inputs to the gate can make at most one transition during evaluation.
- Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL

This behavior is fundamentally different than the static counterpart that always has a low resistance path between the output and one of the power rails.

Properties of Dynamic CMOS Gates reduce area and delay

- Logic function is implemented by the PDN only
- number of transistors is N + 2 (versus 2N for static complementary CMOS)

- Full swing outputs (VOL = GND and VOH = VDD)
- Non-ratioed - sizing of the devices does not affect the logic levels
- Faster switching speeds
- reduced load capacitance due to lower input capacitance (Cin)
- reduced load capacitance due to smaller output loading (Cout)
- no Isc, so all the current provided by PDN goes into discharging CL

Properties of Dynamic Gates, con’t reduce area and delay

- Power dissipation should be better
- consumes only dynamic power – no short circuit power consumption since the pull-up path is not on when evaluating
- lower CL- both Cint (since there are fewer transistors connected to the drain output) and Cext (since there the output load is one per connected gate, not two)
- by construction can have at most one transition per cycle – no glitching

- But power dissipation can be significantly higher due to
- higher transition probabilities
- extra load on CLK

- PDN starts to work as soon as the input signals exceed VTn, so set VM, VIH and VIL all equal to VTn
- low noise margin (NML)

- Needs a precharge clock

C reduce area and delayL

Issues in Dynamic Design 1: Charge LeakageCLK

Clk

Mp

Out

A

Evaluate

VOut

Clk

Me

Precharge

Leakage sources

Dominant component is subthreshold current

CLK reduce area and delay

Impact of Charge Leakage- Output settles to an intermediate voltage determined by a resistive divider of the pull-up and pull-down networks
- Once the output drops below the switching threshold of the fan-out logic gate, the output is interpreted as a low voltage.

Out

C reduce area and delayL

A Solution to Charge Leakage- Keeper compensates for the charge lost due to the pull-down leakage paths.

Keeper

CLK

Mp

Mkp

!Out

A

B

CLK

Me

Same approach as level restorer for pass transistor logic

C reduce area and delayL

Ca

Cb

Issues in Dynamic Design 2: Charge SharingCharge stored originally on CL is redistributed (shared) over CL and CA leading to static power consumption by downstream gates and possible circuit malfunction.

CLK

Mp

Out

A

B=0

CLK

Me

When Vout = - VDD(Ca / (Ca + CL )) the drop in Vout is large enough to be below the switching threshold of the gate it drives causing a malfunction.

Load reduce area and delay

inverter

CLK

y = A B C

a

A

!A

b

Cy=50fF

Cd=10fF

Cb=15fF

B

!B

B

!B

Ca=15fF

Cc=15fF

c

d

!C

C

CLK

Charge Sharing ExampleWhat is the worst case voltage drop on y? (Assume all inputs are low during precharge and that all internal nodes are initially at 0V.)

Vout = - VDD((Ca + Cc)/((Ca+ Cc) + Cy))

= - 2.5V*(30/(30+50)) = -0.94V, so the output drops to -2.5 + 0.94 = -1.56 V

Solution to Charge Redistribution reduce area and delay

Clk

Clk

Mp

Mkp

Out

A

B

Clk

Me

Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

C reduce area and delayL

Issues in Dynamic Design 4: Clock FeedthroughCoupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.

Clk

Mp

Out

A

B

Clk

Me

The danger of the clock feedthrough is that it may cause the normally reverse bias

junction diodes of the precharged transistor to become forward bias.

Clock Feedthrough reduce area and delay

Clock feedthrough

Clk

Out

In1

In2

In3

In &

Clk

Voltage

In4

Out

Clk

Time, ns

Clock feedthrough

6 reduce area and delay

feedthrough

4

f

)

t

l

o

V

(

V

internal node X in PDN

2

0

0

1

2

3

Clock Feedthrough and Charge SharingOut without charge redistribution (Ma off)

out with charge redistribution effects (Maon)

t

(nsec)

Clk reduce area and delay

In

VTn

Out1

V

Out2

Cascading Dynamic Gates issuesV

Clk

Clk

Mp

Mp

Out2

Out1

In

Clk

Clk

Me

Me

Out2 should remain at VDD since Out1 transitions to 0 during evaluation. However, since there is a finite propagation delay for the input to discharge Out1 to GND, the second output also starts to discharge.

t

Only one stage at a time should make a 1 to 0 transition!

The second dynamic inverter turns off (PDN) when Out1 reaches VTn.

Only 0 1 transitions allowed at inputs!

Domino Logic: High performance dynamic CMOS circuits reduce area and delay

CLK

Mp

Mkp

CLK

Mp

Out1

Out2

1 1

1 0

0 0

0 1

In1

In4

PDN

In2

PDN

In5

In3

CLK

Me

CLK

Me

Ensures all inputs to the Domino gate are set to 0 at the end of the precharge period. Hence, the only possible transition during evaluation is 0 -> 1

Additional advantage is that the fan-out of the gate is driven by a static inverter with a low-impedance output that increases the noise immunity.

The buffer also reduces the capacitance of the dynamic output node by separating internal and load capacitances

Domino Logic reduce area and delay

- Solves problem of cascading dynamic gates, but is non-inverting
- Add an inverter between dynamic gates
- Inverter drives the gate’s fanout – increased performance

- Sometimes the inverter is replaced with a more complex static CMOS gate
- Static CMOS gate improves dynamic noise margins

- Add an inverter between dynamic gates
- Solve non-inverting problem by implementing both F and F separately
- Area/power doubles

In reduce area and delayi

Ini

Ini

Ini

PDN

PDN

PDN

PDN

Inj

Inj

Inj

Inj

Why Domino?CLK

In1

CLK

During the precharge phase all input will be turned off because all buffer output are 0.

During the evaluation phase, each buffer output at most can make one transition from 0 to 1.

Like falling dominos!

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