Single event upsets seus soft errors
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Single Event Upsets (SEUs) – Soft Errors. By: Rajesh Garg Sunil P. Khatri Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX. Background. pn junction behavior Electric field Depletion region Energy band diagram of Si

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Single Event Upsets (SEUs) – Soft Errors

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Single event upsets seus soft errors

Single Event Upsets (SEUs) – Soft Errors

By:

Rajesh Garg

Sunil P. Khatri

Department of Electrical and Computer Engineering,

Texas A&M University, College Station, TX


Background

Background

  • pn junction behavior

    • Electric field

    • Depletion region

  • Energy band diagram of Si

    • Energy transferred to Si may excite an electron from valence band to conduction band

    • e-h pairs can be generated


Charge deposition by a radiation particle drift and diffusion

Charge Deposition by a Radiation Particle – Drift and Diffusion

  • Radiation particles - protons, neutrons, alpha particles and heavy ions

  • Reverse biased p-n junctions are most sensitive to particle strikes

  • Charge is collected at the drain nodethrough drift and diffusion

  • Results in a voltage glitch at the drain node

  • System state may change if this voltage glitch is captured by at least one memory element

    • This is called SEU

    • May cause system failure

Radiation Particle

VDD

G

S

D

_

+

n+

n+

Depletion Region

+

_

+

_

E

_

+

_

E

+

VDD - Vjn

_

+

_

+

_

+

p-substrate

B


Charge deposited by a radiation particle

Charge Deposited by a Radiation Particle

  • Linear Energy Transfer (LET) is a common measure of the energy transferred by a radiation particle when it strikes a material

  • Relationship between Q,LET and t

Charge of 1 electron

Therefore the charge deposited by a unit LET (for a track length of 1µm)

So the charge deposited by a radiation strike (in terms of LET and track length) is


Other charge collection mechanisms

Other Charge Collection Mechanisms

  • Bipolar Effect

    • Parasitic bipolar transistor exists in MOSFETs

      • For example, n-p-n (S–B–D) in an NMOS transistor

    • Holes accumulation in an NMOS transistor may turn on this bipolar transistor

  • Alpha-particle Source-drain Penetration (ALPEN)

    • A radiation particle penetrates through both source and drain diffusions


Modeling a radiation particle strike

Modeling a Radiation Particle Strike

  • A radiation particle strike is modeled by a current pulse as

    where: tais the collection time constant

    tb is the ion track establishment constant

  • The radiation induced current always flows from n-diffusion to p-diffusion

  • For an accurate analysis, device level simulationshould be performed


Single event upsets

Single Event Upsets

  • Single Event Upsets (SEUs) or Soft Errors

    • Troublesome for both memories and combinational logic

    • Becoming increasingly problematic even for terrestrial designs

  • A particle strike at the output of a combinational gateresults in a Single Event Transient (SET)

    • If a memory latches wrongvalue -> SEU

  • A particle strike in a memory element may directly lead to an SEU event


Radiation hardening approaches

Radiation Hardening Approaches

  • Can be classified into three categories

    • Device level

    • Circuit level

    • System level

  • Device level – Fault avoidance

    • SOI devices are inherently less susceptible to radiation strikes

      • Low collection volumes

    • Still needs other hardening techniques to achieve SEU tolerance

      • Bipolar effect significantly increases the amount of charge collected at the drain node


System level radiation hardening approaches

System Level Radiation Hardening Approaches

  • Fault detection and fault correction approaches

  • SEU events are detected using built in current sensors (BICS) (Gill et al.)

  • Error correction codes (Gambles et al.)

  • Triple modulo redundancy based approaches (Neumann et. al)

    • Classical way of radiation hardening

    • Area and power overheads are ~200% !!!!


Circuit level hardening

Circuit Level Hardening

  • Fault avoidance approach

  • Gate sizing is done to improve the radiation tolerance of a design (Zhou et al.)

  • Radiation tolerance improves

    • Higher drive capability

    • Higher node capacitance

  • Area, delay and power overheads can be large

    • Selectively harden critical gates


Diode clamping based hardening approach

Diode Clamping based Hardening Approach

  • Approach A - PN Junction Diode based SEU Clamping Circuits

V (out)

Radiation Strike

0.8

1V

0.6

0.4

in

out

0.2

G

0

time

0V

D2

D1

1.4V

V (outP)

0.8

outP

GP

0.6

0.4

Shadow Gate

-0.4V

0.2

Higher VT device

0

time

-0.4


Our radiation hardening approach

Our Radiation Hardening Approach

  • Approach B - Diode-connected Device based SEU Clamping Circuits

V (out)

Radiation Strike

0.8

1V

0.6

0.4

in

out

0.2

G

0

time

0V

D2

D1

Ids

1.4V

V (outP)

0.8

outP

GP

0.6

0.4

-0.4V

0.2

Higher VT device

0

  • Performance of approach A is slightly better than B but with a higher area penalty than B. Therefore, we selected approach B

time

-0.4


Protection performance example

Protection Performance - Example

  • Circuit simulation is performed in SPICE

  • 65nm BPTM model card is used

    • VDD = 1V

    • VTN= | VTP| = 0.22V

  • Radiation strike at output of 2X INV

    • Q = 24 fC

    • ta= 145ps

    • tb= 45ps

  • Approach B is used


Our split output approach

Our Split-output Approach

  • Phase 1

    • Gate level hardening

  • Phase 2

    • Block level hardening

    • Selectively harden critical gates in a circuit

      • To keep area and delay overheads low

      • Reduce SER by 10X


Gate level hardening approach

in

Gate Level Hardening Approach

  • A radiation particle strike at a reverse biased p-n junction results in a current flow from n-type diffusion to p-type diffusion

    • A gate constructed using only PMOS (NMOS) transistors cannot experience 1 to 0 (0 to 1) upset

Radiation Particle

inp

out1p

inp & inn

VDD - VTN

out2

out2

out1

out1n

out1p

|VTP|

INV1

INV2

out1n

Radiation Particle

inn

out2

INV2

INV1

Static Leakage Paths


Our gate level hardening approach

inp & inn

VDD - VTN

out1n

out1p

|VTP|

out2

Our Gate Level Hardening Approach

Low VT transistors

inp

inp

out1p

out1p

X

out2

out2

out1n

X

inn

out1n

Leakage currents are lower by ~100X

inn

Radiation Tolerant Inverter

Modified Inverter


Radiation tolerant inverter

Radiation Tolerant Inverter

Radiation Particle Strike

inp

X

Radiation Particle Strike

M8

M2

X

out1p

inp & inn

X

M4

X

M6

out1n

out2

out1p

X

M5

out2

M3

out1n

The voltage at out2 is unaffected

X

M7

M1

A radiation particle strike at any node of the first inverter (radiation tolerant inverter) does not affect the voltage at out2

inn


Radiation tolerant inverter1

Radiation Tolerant Inverter

  • Radiation particle strike at the outputs of INV1

  • Implemented using 65nm PTM with VDD=1V

  • Radiation strike: Q=150fC, ta=150ps & tb=38ps

inp

out1p

out2

out1n

inn

INV1


Block level radiation hardening

Block Level Radiation Hardening

  • 100% SEU tolerance can be achieved by hardening all gates in a circuit but this will be very costly

  • Protect only sensitive gates in a circuit to achieve good SEU tolerance or coverage

    • We obtain these sensitive gates using Logical Masking

    • PLM (G) is the probability that the voltage glitch due to a radiation particle strike gets logically masked

    • PSen(G) = 1 – PLM(G)

    • If we want to protect only 2 gates then we should to protect Gates 1 and 3 to maximize SEU tolerance

      • Gate 3 is the most sensitive

P1 = 0.25 P0 = 0.75

0

0

For all inputs P1 = 0.5 P0 = 0.5

1

1

1

3

2

1

→ 1

0

P1 = 0.5 P0 = 0.5

Radiation Particle


Block level radiation hardening1

Block Level Radiation Hardening

  • Obtained PSen for all gates in a circuit using a fault simulator

  • Sort these gates in decreasing order of their PSen

  • Harden gates until the required coverage is achieved

    • Coverage is a good estimate for SER reduction (Zhou et al.)

  • Gates at the primary output of a circuit need to be hardened since PSen = 1 for these gates

  • The dual outputs of the hardened gates at the primary outputs drive the dual inputs of an SEU tolerant flip-flip (such as the flip-flop proposed by Liu et al.)


Critical charge q cri

Critical Charge (Qcri)

  • Minimum amount of charge which can result in an SEU event

  • Our hardened gates can tolerate a large amount of charge dumped by a radiation particle

    • Operating frequency of circuit determines Qcri

  • Qcriis the amount of charge which results in a voltage glitch of pulse width T

CLK

in

out1n

out1p

out2

t1

T + t1

2T + t1


Experimental results

Experimental Results

  • We implemented a standard cell library L using a 65nm PTM model card with VDD = 1.0V

    • Implemented both regular and hardened versions of all cell types

  • Applied our approach to several ISCAS and MCNC benchmark circuits

  • We implemented

    • A tool in SIS to find the sensitive gates in a circuit

    • An STA tool to evaluate the delay of a hardened circuit obtained using our approach

    • Layouts were created for all gates in our library for both regular and hardened versions


Experimental results1

Experimental Results

  • Average results over several benchmark circuits mapped for area and delay optimality

  • Our SEU immune gates can tolerate high energy radiation particle strikes

  • Critical charge is extremely high (>520fC) for all benchmark circuits

    • Suitable for space and military application because of the presence of large number of high energy radiation particles


Comparison our hardening approach

Comparison Our Hardening Approach

  • Our approach is suitable for radiation environments with high energy particles


Sram hardening

SRAM Hardening

  • Decrease recovery time

  • Slow down feedback path

    • Insert resistors in the feedback paths

  • Resistor

    • Polysilicon

    • Gated

    • Increases write delay


Conclusions

Conclusions

  • SEUs are troublesome for both memories and combinational logic

    • Becoming increasingly problematic even for terrestrial designs

  • Applications demand reliable systems

    • Need to efficiently design radiation hardening approaches for both combinational and sequential elements

    • Also need efficient analysis techniques to estimate SER of complex circuits

      • SEU susceptibility can be checked during design phase

      • Reduce the number of design iterations


Thank you

Thank You


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