The World’s Fastest CMOS FPGA for Commercial and Extreme Environments
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The World’s Fastest CMOS FPGA for Commercial and Extreme Environments. Achronix Technology and Product Overview Presented: November 15, 2005 – NASA Goddard Space Flight Center. Legal Disclaimers. Safe Harbor Notice

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Achronix technology and product overview

The World’s Fastest CMOS FPGA for Commercial and Extreme Environments

Achronix Technology and Product Overview

Presented: November 15, 2005 – NASA Goddard Space Flight Center


Legal disclaimers

Legal Disclaimers

Safe Harbor Notice

This document is not a prospectus and is for informational purposes only. The document contains "forward looking statements" which are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Forward looking statements are generally preceded by words such as "will," "expects," or "anticipates." Investors are cautioned that all forward-looking statements in this release involve risks and uncertainty, including without limitation the risk that the Company's products may not be available according to the current schedule.

Securities Act of 1933 and Blue Sky Notice

Nothing contained herein shall be deemed to create an “offer” to sell interests or securities, public or private, as such terms is used and construed in and under the Securities Act of 1933 or the Securities Exchange Act of 1934, or any related law or any “Blue Sky” law of any State.

Export Control Notice

The information contained in this document is not considered Export Controlled by the United States, as defined in the International Trafficking in Arms Regulations (ITAR), and is therefore exempt from restrictions of disclosure to non-US Persons.


Agenda

Agenda

  • Company Overview

  • Overview of Asynchronous Circuits

  • Achronix Technology & Solution Overview

  • Product Architecture and Specifications


Achronix semiconductor overview

Achronix Semiconductor Overview

History

Product Space

Status and Goals

  • Founded 2004 in Ithaca, NY

  • Founders include original developers of technology at Cornell Univ. - Dr. Rajit Manohar, Dr. Clinton Kelly, IV, Dr. Virantha Ekanayake - and John Lofton Holt

  • All founders except Dr. Ekanayake are full time employees of Achronix presently

  • Financed with owners capital to date. Company is currently working with several private equity groups to fund production in 2006.

  • We make the world’s fastest Field Programmable Gate Arrays (FPGAs) in two product lines:

    • Achronix-ULTRA: GHz Speed Ultra high performance FPGA

    • Achronix-XTREME: GHz Speed Extreme environment (temperature and radiation) FPGA

  • Competitors:

    • FPGA Vendors: Xilinx, Altera, Actel, Lattice, etc.

    • ASIC Vendors: LSI Logic, Fujitsu, IBM, Hitachi

  • Completed first successful prototype of product in early 2005, a 674 MHz FPGA fabricated in TSMC 180nm CMOS

  • Completed second prototype in October 2005 (due back in January 2006), a 1+GHz FPGA fabricated in ST Microelectronics 90nm CMOS

  • Goal:

    • Ship first product in 2006

    • Achieve profitability in 2007

Achronix’ technology is based on asynchronous logic


Our goal is to build ghz speed fpgas for commercial and extreme environments

Our goal is to build GHz-speed FPGAs for commercial and extreme environments

Achronix Key Goals

  • Ultra fast Speed

    • Support system throughputs in the 1+GHz (2006) to 2.5 GHz (2008) range through our asynchronous FPGA fabric

  • Competitive Density and Power Performance

    • While operating at GHz speeds, provide competitive density and power performance to state of the art devices from Xilinx, Altera, Actel, and Lattice

  • Synchronicity and Interoperability

    • At the system level, look and feel just like a traditional synchronous FPGA from Xilinx, Altera, Actel, Lattice, and others by surrounding our fabric with traditional synchronous I/Os

  • Support the Existing EDA Landscape

    • Support existing EDA tools used by FPGA and ASIC designers to ensure that our products can be integrated easily and immediately and replace slower parts from or competitors

*Source: Simulations of Achronix 90nm design. Real results to be determined in January 2006


Agenda1

Agenda

  • Company Overview

  • Overview of Asynchronous Circuits

  • Achronix Technology & Solution Overview

  • Product Architecture and Specifications


Asynchronous circuits are not new in the research community or in the commercial world

Asynchronous circuits are not new in the research community or in the commercial world

Design of first GHz asynchronous FPGA (Achronix)

Introduction of fastest reconfigurable logic module in CMOS (Cornell University/Achronix)

Fabrication of fastest asynchronous microprocessor (Caltech)

First theory of an asynchronous computational machine (Princeton)

1946 … 1969 … … … 1989 1998 2003 20042005

Fabrication of first asynchronous microprocessor (Caltech)

Introduction of first commercial RS232 asynchronous serial interface

(Bell)

Introduction of first asynchronous commercial product (Fulcrum Microsystems)

Introduction of first microprocessor for sensor networks (Cornell University/Achronix)

Introduction of asynchronous interface logic in next generation Itanium processor

(Intel)

*Source: A.W. Burks, H.H. Goldstein, and John von Neumann. Preliminary discussion of, the logical design of an electronic computing instrument. Institute for Advanced, Study, Princeton, N.J., June 1946., Wikipedia “RS232”, Manohar “The Impact of Ascynchrony on Computer Architecture”, 1998, Naffziger, et al, “The Implementation of a 2-CoreMulti-Threaded Itanium Family Architecture”, ISSCC 2005


Achronix technology and product overview

Asynchronous circuits operate in a fundamentally different way that their traditional synchronous counterparts

Asynchronous Circuit Behavior:Continuous Time, Continuous Voltage

Traditional Synchronous Circuit Behavior:Discrete Time, Discrete Voltage

Clock

DATA 1

DATA

DATA 0

Sender

Receiver

Sender

Receiver

ACK

DATA “1”

DATA “1”

DATA “0”

DATA “0”

CLK

ACK


Achronix technology and product overview

This asynchronous method of operation allows computations to be “pipelined”, which reduces the complexity of operations, and facilitates more efficient parallel computation

a:= f(x)

b:= g(a)

c:= h(b)

c:= h(g(f(x)))

Synchronous Computation

Asynchronous Computation

The result: Faster execution, no registers required to store values, no power wasted waiting for previous instructions to complete


Achronix technology and product overview

The asynchronous approach has numerous advantages over traditional synchronous circuits, and significant advantages in extreme environments, but there are challenges

Asynchronous Advantages

  • Speed: Circuit speed is no longer limited by a clock

  • Power: Because circuits only operate when they need to, standby power is dramatically reduced and operating power is highly optimized

  • Redundancy: Data is encoded, therefore redundancy can be exploited to locate permanent faults and tolerate transient faults

  • Scaling: Circuits scale more efficiently as there are not clock distribution issues and NO GLOBAL SIGNALS (As the circuits scale, density increases versus synchronous counterparts)

  • Delay Insensitive: Circuits do not depend on, or make assumptions about delays.

Asynchronous Challenges

  • Density: Increased number of wires for logic functionality results in small area penalty in individual circuits (mitigated by lack of clock distribution logic required)

  • Synchronous Interfaces: The world of electronics is synchronous, so asynchronous systems must have synchronous “edges” to interoperate with other synchronous devices in a system

The Achronix solution leverages the benefits while addressing the challenges to present a product that can be used by customers today, using their existing designs and infrastructure


Agenda2

Agenda

  • Company Overview

  • Overview of Asynchronous Circuits

  • Achronix Technology & Solution Overview

  • Product Architecture and Specifications


Achronix technology and product overview

Achronix has already built a 180nm prototype that operates at 674MHz system throughput, over twice as fast as similar devices from FPGA industry leaders

180nm Prototype Layout

180nm Prototype Performance

180nm Prototype Die Photograph

90nm 1.8V Xilinx Virtex-4 maximum internal clock speed (system throughput significantly lower)

180nm Achronix Measured system throughput of 674 MHz at room temperature at nominal operating voltage of 1.8V

130nm 1.8V Xilinx Virtex-2 maximum internal clock speed (system throughput significantly lower)

Source: Xilinx Virtex-II and Virtex-4 data sheets. “Twice as fast” is conservative considering system throughput of Achronix device versus maximum throughput (25% - 80%of internal clock speed) of Xilinx devices.


Achronix technology and product overview

The 90nm prototype (October 2005) will operate at 1+GHZ speeds at lower power and comparable densities as state-of-the-art FPGAs from Xilinx, Altera, Actel, and others

Achronix Performance

  • Speed:

    • 180nm prototype: 674 MHz (measured)

    • 90nm test chip: 1.4 - 1.6 GHz (Jan 2006)

  • Power (based on 180nm prototype):

    • Consumes the same amount of power as a conventional FPGA operating at 33%the speed (Two thirds less energy per cycle)

  • Density (based on 180nm prototype):

    • Competitive with existing state-of-the-art devices from industry leaders

    • Will be monotonically higher in 90nm test chip

No need to migrate to these processes now – Maybe ever

Simulated for 90nm test chip layout (due back from Fab in Jan 06)

Measured 674MHz with 180nm prototype

*Source: SOCCentral.com Datasheet archive and Xilinx, Altera, Actel, Lattice Datasheets. Power not compared because reliable metrics unavailable, trends likely to mimic speed and density, 45nm and 32nm figures estimated based on trend analysis Years expected for 65,45,and 32nm processes courtesy of “ITRS Roadmap for Semiconductors 2004”


Achronix technology and product overview

We believe that these levels of speed will be unmatched by Xilinx, Altera, Actel, Lattice, and even most ASIC vendors regardless of which fabrication processes are used

The Achronix Differentiators: SPEED and COSTBy offering unprecedented speed in an economical 90nm process with competitive power and density performance, we will take the high performance FPGA market

*Source: SOCCentral.com Datasheet archive and Xilinx, Altera, Actel, Lattice Datasheets. Power not compared because reliable metrics unavailable, trends likely to mimic speed and density, 45nm and 32nm figures estimated based on trend analysis


Asynchronous dataflow computation

Asynchronous dataflow computation

  • Fundamentally, our FPGA operates like a traditional FPGA, but using a different model

    • Asynchronous dataflow

    • Tokens hold data values

    • Tokens flow through pipeline stages

    • Pipeline stages transform token values

  • Performance

    • Latency = input to output delay

    • Throughput = rate at which tokens are processed

  • Computation is data-driven not clock-driven

    • Power savings when circuits are not doing computation

    • Every gate is “clock gated”


Fundamentally the components of the achronix fpga are identical to altera and xilinx

Fundamentally, the components of the Achronix FPGA are identical to Altera and Xilinx

Switch Boxes (SB) routes channels between logic block

“Logic Blocks” contain the reprogrammable logic, typically in the form of a 4-input Look Up Table (LUT) and other combinational logic

The “Interconnect” provides the infrastructure for communication between switch boxes on the FPGA


Achronix technology and product overview

The Achronix FPGA, both at the architectural level and at the logic block level, has a very similar design to typical Xilinx and Altera FPGAs

Achronix Architecture and Logic Block Diagram

Xilinx Virtex-4 Architecture and Logic Block Diagram

Altera Stratix-II Architecture and Logic Block Diagram

High speed synchronous I/Os

Dedicated multiplier blocks

Embedded RAM modules

Asynchronous high speed programmable logic cells

Four-Input

LUT

State/

Conditional

Unit (Token)

4-input LUT plus Conditional unit is called a “logic block” and is very similar to a Xilinx “LC”

Entire unit is called “Slice”

Entire unit is called “ALM – Advanced Logic Module”

4-input LUT plus register is called “LC – Logic Cell”

4-input LUT plus register is called “LE – Logic Element”

*Source: Altera Stratix-II datasheet, Xilinx Virtex-4LX Datasheet


Achronix technology and product overview

The detailed circuits that comprise our logic blocks are similar to Xilinx’ “LC” Logic Cells and Altera’s “LE” Logic Elements

Components present in Xilinx LC or Altera LE (plus clock distribution and register logic)


Our aggressive pipelined interconnect significant increases our performance

Our aggressive pipelined interconnect significant increases our performance

  • Long wires through switches have poor performance

    • Limits performance of traditional FPGA architectures

  • ASIC solution: add repeaters/buffers

    • Improves signal integrity, latency

  • Aggressive solution

    • Add pipeline stages to keep throughput high

    • Synchronous: requires complete design re-timing because data arrives at different clock tick

  • Asynchronous pipelining

    • Adding pipeline stage is “almost always” safe; for deterministic computation it is always safe

*Source: [MM98] R. Manohar and A.J. Martin. “Slack Elasticity in Concurrent Computing.” Proc. 4th International Conference on the Mathematics of Program Construction, Lecture Notes in Computer Science 1422, June 1998.


Achronix technology and product overview

Our switch box architecture is nearly identical to a conventional switch box, but when combined with our interconnect, dramatically increases our speed

Traditional Synchronous “Layered” Interconnect

Achronix Asynchronous Pipelined Interconnect

Traditional FPGA Deficiencies

Achronix Advantages

  • Increased Latency: Adding pipeline stage encounters one cycle of latency

  • Interconnect Timing: Requirement of matching numbers of flip-flops after place and route makes pipelining impossible

  • Increased Complexity: Long-haul routes with increased switch box complexity fundamentally limits complexity and density

  • Reduced Latency: Adding pipeline stage adds 0.125 cycles of latency

  • Pipelined Interconnect: Token-based model enables variations in interconnect hop counts, minimizing latency in the interconnect

  • Modular Design: Elimination of long-haul routes and global signals enables massive scalability

*Source: W. Tsu et al. "HSRA: High-Speed Hierarchical Synchronous Reconfigurable Array." Proc. FPGA 1999


Achronix technology and product overview

We tested our 180nm prototype using a variety of well known FPGA benchmarks, and achieved unusually high throughput across a wide range of benchmarks

Achronix Measured Performance (180nm)

Altera Stratix-II Measured Performance (90nm)

Achronix Average 636 MHz

Altera Stratix-II Average 334 MHz

Achronix Average 94.4% Utilization

Altera Stratix-II Average 66.9% Utilization

*Source: Altera Stratix-II “Design Building Block Performance”, August 2005, No data available for Xilinx, but performance is comparable to Altera Stratix-II


Achronix technology and product overview

Using the same asynchronous circuit core in 90nm CMOS technology, Achronix has designed an identical FPGA that operates at over 1GHz system throughput

180nm and 90nm Prototype Performance

90nm Simulation Data

Simulations of 90nm prototype range from 1.4 – 1.6GHz system throughput

Measured 674MHz system throughput with 180nm prototype

Compensated simulations predict performance in the 1.4-1.6 GHz range. We will verify the actual system throughout when the 90nm devices return from fabrication in January 2006, but we conservatively expect performance well over 1GHz.


Achronix technology and product overview

We expect this prototype to perform at an average throughput of at least 1.3GHz (based on simulations)

Achronix Expected Performance (90nm)

Altera Stratix-II Measured Performance (90nm)

Achronix Average 1.32 GHz

Altera Stratix-II Average 334 MHz

Achronix Average 94.4% Utilization

Altera Stratix-II Average 66.9% Utilization

*Source: Altera Stratix-II “Design Building Block Performance”, August 2005


Our architecture also allows for temperature insensitivity

Our architecture also allows for temperature insensitivity

  • Key features of class of asynchronous circuits we are using

    • Tolerant to arbitrary variations in gate delay

    • Tolerant to conductivity changes in wires

  • CMOS devices have a wide operating range

  • Nominal net effect of temperature change

    • Delay change

    • We have no PLLs, oscillators, or other analog circuits for clock distribution

  • Asynchronous circuits are naturally temperature insensitive

    • Change in temperature impacts performance, but circuits still operate correctly


Temperature insensitivity

Temperature Insensitivity


Temperature insensitivity1

Temperature Insensitivity


Measured peak performance with temperature 180nm

Measured Peak Performance with Temperature (180nm)


Radiation tolerance will be achieved by a radhard by design approach on soi

Radiation tolerance will be achieved by a RADHARD by design approach on SOI

  • Technology + design approach

  • Asynchronous self-correction for event upsets

    • When a gate has an event upset (logic fault), we can wait for the upset to self-correct and locally stall the computation

  • Circuits are encoded

    • Data representation used has redundancy

    • Redundancy can be used for cross-checking values with a simple circuit technique

  • Deep sub-micron SOI allows us to use “RADHARD by design” methods

    • Gate layout geometries

  • We are investigating this experimentally in 2006, but plan to support 100krad – 300krad TID


Agenda3

Agenda

  • Company Overview

  • Overview of Asynchronous Circuits

  • Achronix Technology & Solution Overview

  • Product Architecture and Specifications


Achronix technology and product overview

Since our announcement about our prototype in September we have spoken to over 20 potential customers. This has driven our architecture road map.

Achronix 90nm Product Road Map

Predicted Performance – 90nm

Speed Focus

140% increased in speed

30% reduction in power consumption

30% increase in density

50% Risk

Shipping in 1H2008

Power Focus

10% decrease in speed

65% reduction in power consumption

40% increase in density

25% Risk

Shipping in 2H2007

No decrease in speed

No reduction in power consumption

40% increase in density

25% Risk

Shipping in 1H2008

Density Focus


Achronix technology and product overview

Using our familiar architecture with an asynchronous core, our first product will significantly outperform industry leaders’ products in terms of speed and power

Power Performance (Historical Data for Asynchronous Circuits)

Achronix expected circuit power performance: 36%-63% lower

Speed Performance

Density Performance (Expected @ 90nm)

Achronix density band

…and while our unit density is lower, our ability to scaledensity enables us to build devices with comparable density as industry leaders, but at lower cost

*Source: Achronix testing of 180nm device, Achronix simulations of 90nm device, Pricing and density data from Xilinx and Altera Websites and AVNET list pricing from website


Achronix technology and product overview

Since we can scale our density with die size, our supported density becomes a business decision for our first lines of products, rather than a technical challenge

Target Product Specs

  • Achronix-ULTRA Specs

    • Speed: 1.4 – 1.6 GHz throughput

    • Power: Not a pricing factor. Will be lower than Altera Stratix-II and Xilinx Virtex-4

    • Density: 1M to 1.5M AEG (80k-120k LUTs)

    • Op. Temp = -264 to + 130 C

  • Achronix-XTREME Specs

    • Speed: 1.0 – 1.2GHz throughput

    • Power: Not a pricing factor. Will be lower than Actel RTAX-S

    • Density: 1+M AEG (80k LUTs)

    • Op. Temp = -264 to + 130 C

    • Radiation Tolerance = 100-300 krad

Achronix-ULTRA density-pricing band

Achronix-XTREME density-pricing band


Achronix technology and product overview

Because the Achronix FPGA is based on a familiar architecture, and utilizes synchronous interfaces, customers can leveraging existing software infrastructure

Achronix Tool Chain

Achronix software development efforts will focus on the entire tool chain, but particularly on these component in 2006

Accepts input from any type of description language

Example: Celoxica Interface

Example: Synplicity/Cadence/Mentor Graphics Interface


This aggressive hardware and software strategy will allow us to accomplish our key goals

This aggressive hardware and software strategy will allow us to accomplish our key goals

Achronix Key Goals

  • Ultra fast Speed

    • Support system throughputs in the 1 GHz (2006) to 2.5 GHz (2008) range through our novel asynchronous FPGA fabric

  • Competitive Density and Power Performance

    • While operating at GHz speeds, provide competitive density and power performance to state of the art devices from Xilinx, Altera, Actel, and Lattice

  • Synchronicity and Interoperability

    • At the system level, look and feel just like a traditional synchronous FPGA from Xilinx, Altera, Actel, Lattice, and others by surrounding our fabric with traditional synchronous I/Os

  • Support the Existing EDA Landscape

    • Support existing EDA tools used by FPGA and ASIC designers to ensure that our products can be integrated easily and immediately and replace slower parts from or competitors

We would like to understand what other specific features/goals that the extreme environment community would like to see in our product, and when you would like to see the product

*Source: Simulations of Achronix 90nm design. Real results to be determined in January 2006


Achronix technology and product overview

Achronix Semiconductor Corporation

427 East Seneca Street, Suite 100

Ithaca, NY, 14850

USA

Phone: +1.877.GHZ.FPGA (877.449.3742)

Fax: +1.413.280.9887

Internet: http://www.achronix.com

Email:[email protected]


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