The pink , blue , green slide

1. The pink, blue, green slide • Current instruction in EX stage: pink • Previous instruction in _____ stage:blue • Previous to previous instruction in _____ stage:green MEM WB

2. 0 1 IF/ID ID/EX EX/MEM MEM/WB PC 0 1 2 Registers ForwardA Instruction memory ALU 0 1 2 Data memory 1 0 ForwardB Rt Rd The pink, blue, green slide

3. 0 1 IF/ID ID/EX EX/MEM MEM/WB PC 0 1 2 Registers ForwardA Instruction memory ALU 0 1 2 Data memory 1 0 ForwardB Rt Rd The pink, blue, green slide ID/EX.RegisterRt EX/MEM.RegisterRt MEM/WB.RegisterRt

4. EX/MEM data hazards • Example: • sub $2, $1, $3 • and $12, $2, $5 • Where does it happen? • between current instruction (EX stage) and previous instruction (MEM stage) • When does it happen? • previous instruction will write to register R, and • R is an ALU source in current instruction.

5. EX/MEM data hazard equations if (EX/MEM.RegWrite = 1 and EX/MEM.RegisterRd = ID/EX.RegisterRs) then ForwardA = 2 Similarly, if (EX/MEM.RegWrite = 1 and EX/MEM.RegisterRd = ID/EX.RegisterRt) then ForwardB = 2

6. MEM/WB data hazards • Example: • sub $2, $1, $3 • … • and $12, $2, $5 • Where does it happen? • between current instruction (EX stage) and previous to previous instruction (WB stage) • When does it happen? • previous to previous instruction will write to register R, and • R is an ALU source in current instruction.

7. MEM/WB data hazard equations if (MEM/WB.RegWrite = 1 and MEM/WB.RegisterRd = ID/EX.RegisterRs) then ForwardA =1 Similarly, if (MEM/WB.RegWrite = 1 and MEM/WB.RegisterRd = ID/EX.RegisterRt) then ForwardB =1

8. Oh, but wait… • What if a register is updated twice in a row? add $1, $2, $3 add $1, $1, $4 sub $5, $5, $1 • This is a ________________ hazard EX/MEM

9. Correct MEM/WB data hazard equations if (MEM/WB.RegWrite = 1 and MEM/WB.RegisterRd = ID/EX.RegisterRs and (EX/MEM.RegisterRd≠ID/EX.RegisterRs or EX/MEM.RegWrite = 0)) then ForwardA =1 Similarly, if (MEM/WB.RegWrite = 1 and MEM/WB.RegisterRd = ID/EX.RegisterRt and (EX/MEM.RegisterRd≠ID/EX.RegisterRt or EX/MEM.RegWrite = 0)) then ForwardB =1

10. 0 1 PC 0 1 2 0 1 2 0 1 Forwarding Unit Complete pipelined datapath...so far ID/EX EX/MEM WB Control MEM/WB M WB IF/ID EX M WB Read register 1 Read data 1 Addr Instr Read register 2 ALU Zero ALUSrc Write register Read data 2 Result Address Instruction memory Data memory Write data Registers Write data Read data Instr [15 - 0] 1 0 RegDst Extend Rt Rd EX/MEM.RegisterRd Rs MEM/WB.RegisterRd

11. MIPS and Pipelining • Each MIPS instruction writes to at most one register • much harder to forward multiple registers • Writes happen near the end of the pipeline wouldn’t forwarding be unnecessary if writes happened early? • early write-back implies less chance to intervene • also, even earlier computation, so more forwarding paths • No structural hazards • A structural hazard occurs when an instruction cannot execute because the hardware it needs is being used • E.g. what if we had a single memory ?

12. PCSource Shift left 2 ALUSrcA PC ALU Out IorD RegDst IRWrite RegWrite [31-26] [25-21] [20-16] [15-11] [15-0] Read register 1 Read data 1 ALU Read register 2 Zero Address Read data 2 Instruction register 0 1 2 3 Result 0 M u x 1 0 M u x 1 0 M u x 1 0 M u x 1 0 M u x 1 Write register Memory ALUOp Memory data register A Write data Registers Write data Mem Data B Sign extend MemToReg The multicycle datapath PCWrite MemRead 4 MemWrite ALUSrcB

13. EX/MEM data hazards • Example: • addi $1, $2, $5 • and $2, $1, $3 ID/EX.RegisterRs EX/MEM.RegisterRs MEM/WB.RegisterRs ID/EX.RegisterRt EX/MEM.RegisterRt MEM/WB.RegisterRt ID/EX.RegisterRd EX/MEM.RegisterRd MEM/WB.RegisterRd ID/EX.RegWrite EX/MEM.RegWrite MEM/WB.RegWrite