Tackling the search for lepton flavor violation with ghz waveform digitizing using the drs chip
This presentation is the property of its rightful owner.
Sponsored Links
1 / 76

Tackling the search for Lepton Flavor Violation with GHz waveform digitizing using the DRS chip PowerPoint PPT Presentation


  • 62 Views
  • Uploaded on
  • Presentation posted in: General

Tackling the search for Lepton Flavor Violation with GHz waveform digitizing using the DRS chip. Stefan Ritt Paul Scherrer Institute, Switzerland. Agenda. MEG Experiment searching for m e g down to 10 -13. DRS1. DRS2. DRS3. Motivation. Why should we search for m  e g ?.

Download Presentation

Tackling the search for Lepton Flavor Violation with GHz waveform digitizing using the DRS chip

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


Tackling the search for lepton flavor violation with ghz waveform digitizing using the drs chip

Tackling the search forLepton Flavor Violationwith GHz waveform digitizing using the DRS chip

Stefan Ritt

Paul Scherrer Institute, Switzerland


Agenda

Agenda

MEG Experiment searching

for me g down to 10-13

DRS1

DRS2

DRS3

Fermilab


Motivation

Motivation

Why should we search for m  e g ?


The standard model

The Standard Model

Generation I II III

*) Yet to be confirmed

Fermilab


The success of the sm

The success of the SM

  • The SM has been proven to be extremely successful since 1970’s

    • Simplicity (6 quarks explain >40 mesons and baryons)

    • Explains all interactions in current accelerator particle physics

    • Predicted many particles (most prominent W, Z )

  • Limitations of the SM

    • Currently contains 19 (+10) free parameters such as particle (neutrino) masses

    • Does not explain cosmological observation such as Dark Matter and Matter/Antimatter Asymmetry

Today’s goal is to look for physics beyond the standard model

CDF

Fermilab


Beyond the sm

  • High Energy Frontier

  • Produce heavy new particles directly

  • Heavy particles need large colliders

  • Complex detectors

  • High Precision Frontier

  • Look for small deviations from SM (g-2)m , CKM unitarity

  • Look for forbidden decays

  • Requires high precision at low energy

Beyond the SM

Find New Physics

Beyond the SM

Fermilab


The muon

The Muon

  • Discovery: 1936 in cosmic radiation

  • Mass: 105 MeV/c2

  • Mean lifetime: 2.2 ms

Seth Neddermeyer

ne

W-

e-

Carl Anderson

≈ 100%

m-

nm

0.014

< 10-11

led to Lepton Flavor Conservationas “accidental” symmetry

Fermilab


Lfv and neutrino oscillations

g

W-

m-

e-

nm

ne

LFV and Neutrino Oscillations

  • Neutrino Oscillations  Neutrino mass  m  e g possible even in the SM

 LFV in the charged sector is forbidden in the Standard Model

n mixing

Fermilab


Lfv in susy

g

g

W-

m-

e-

m-

e-

nm

ne

LFV in SUSY

  • While LFV is forbidden in SM, it is possible in SUSY

≈ 10-12

Current experimental limit: BR(m e g) < 10-11

Fermilab


History of lfv searches

m→ e g

mA→ eA

m→ eee

History of LFV searches

  • Long history dating back to 1947!

  • Best present limits:

    • 1.2 x 10-11 (MEGA)

    • mTi → eTi < 7 x 10-13 (SINDRUM II)

    • m → eee < 1 x 10-12 (SINDRUM II)

  • MEG Experiment aims at 10-13

  • Improvements linked to advancein technology

cosmic m

10-1

10-2

10-3

10-4

10-5

stopped p

10-6

10-7

m beams

10-6

stopped m

10-9

10-10

10-11

SUSY SU(5)

BR(m e g) = 10-13 mTi  eTi = 4x10-16BR(m eee) = 6x10-16

10-12

10-13

MEG

10-14

10-15

1940 1950 1960 1970 1980 1990 2000 2010

Fermilab


Current susy predictions

ft(M)=2.4 m>0 Ml=50GeV 1)

Current SUSY predictions

current limit

MEG goal

tan b

“Supersymmetric parameterspace accessible by LHC”

  • J. Hisano et al., Phys. Lett. B391 (1997) 341

  • MEGA collaboration, hep-ex/9905013

W. Buchmueller, DESY, priv. comm.

Fermilab


Experimental method

Experimental Method

How to detect m  e g ?


Decay topology m e g

Decay topology m  e g

52.8 MeV

m e g

N

g

52.8 MeV

m

180º

Eg[MeV]

10

20

30

40

50

60

e

N

52.8 MeV

  • m→ e g signal very clean

  • Eg = Ee = 52.8 MeV

  • qge = 180º

  • e and g in time

52.8 MeV

Ee[MeV]

10

20

30

40

50

60

Fermilab


Accidental background

g

g

n

m

n

n

n

m

e

e

“Accidental” Background

Background

m e g

g

m  e nn

m

Annihilation

in flight

180º

e

m  e nn

  • m→ e g signal very clean

  • Eg = Ee = 52.8 MeV

  • qge = 180º

  • e and g in time

Good energy resolution

Good spatial resolution

Excellent timing resolution

Good pile-up rejection

Fermilab


Previous experiments

How can we achieve a quantum step in detector technology?

Previous Experiments

Fermilab


Collaboration

Collaboration

  • ~70 People (40 FTEs) from five countries

Fermilab


Paul scherrer institute

Proton Accelerator

Swiss Light Source

Paul Scherrer Institute

Fermilab


Psi proton accelerator

PSI Proton Accelerator

Fermilab


Meg beam line

MEG beam line

Rm ~ 1.1x108m+/s at experiment

e+

m+

s ~ 10.9 mm

m+

Fermilab


Liquid xenon calorimeter

H.V.

Refrigerator

Signals

Cooling pipe

Vacuum

for thermal insulation

Al Honeycomb

Liq. Xe

window

PMT

filler

Plastic

1.5m

Liquid Xenon Calorimeter

  • Calorimeter: Measure g Energy, Positionand Time through scintillation light only

  • Liquid Xenon has high Z and homogeneity

  • ~900 l (3t) Xenon with 848 PMTs(quartz window, immersed)

  • Cryogenics required: -120°C … -108°

  • Extremely high purity necessary:1 ppm H20 absorbs 90% of light

  • Currently largest LXe detector in theworld: Lots of pioneering work necessary

g

m

Fermilab


Tackling the search for lepton flavor violation with ghz waveform digitizing using the drs chip

  • Use GEANT to carefully study detector

  • Optimize placement of PMTs according to MC results

Fermilab


The complete meg detector

The complete MEG detector

Fermilab


Current resolution estimates

Current resolution estimates

Fermilab


Meg current status

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

R&D

Set-up

Engineering

Data

Taking

MEG Current Status

  • Goal: Produce “significant” result before LHC

  • R & D phase took longer than anticipated

  • Detector has been completed by theend of 2007

  • Expected sensitivity in 2008: 2 x 10-12(current limit: 1 x 10-11)

http://meg.psi.ch

Fermilab


Pile up in the dc system

Pile-up in the DC system

  • Pile-up can severely degrade the experiment performance ( MEGA Experiment) !

  • Traditional electronics cannot detect pile-up

TDC

Need fullwaveform digitization

> 100 MHz to reject pile-up

Discriminator

Measure Time

Amplifier

hits

Moving average baseline

Fermilab


Beam induced background

Beam induced background

  • 108m/s produce 108 e+/s produce 108g/s

Cable ductsfor Drift Chamber

Fermilab


Pile up in the lxe calorimeter

m

e

Pile-up in the LXe calorimeter

n

PMT

sum

0.511 MeV

meg

radiativemuon

decay

51.5 MeV

50 51 52

E[MeV]

t

~100ns

(menn)2 + g

  • g’s hitting different parts of LXe can be separated if > 2 PMTs apart (15 cm)

  • Timely separated g’s need waveform digitizing > 300 MHz

  • If waveform digitizing gives timing <100ps, no TDCs are needed

g

e

m

Fermilab


Requirements summary

Requirements summary

  • Need 500 MHz 12 bit digitization for Drift Chamber system

  • Need 2 GHz 12 bit digitization for Xenon Calorimeter + Timing Counters

  • Need 3000 Channels

  • At affordable price

Solution: Develop own“Switched Capacitor Array” Chip

Fermilab


The domino principle

The Domino Principle

0.2-2 ns

Inverter “Domino” ring chain

IN

Waveform

stored

Out

FADC

33 MHz

Clock

Shift Register

“Time stretcher” GHz  MHz

Keep Domino wave running in a circular fashion and stop by trigger Domino Ring Sampler (DRS)

Fermilab


Switched capacitor array

Switched Capacitor Array

  • Cons

    • No continuous acquisition

    • No precise timing

    • External (commercial) FADC needed

  • Pros

    • High speed (~5 GHz) high resolution (~12 bit equiv.)

    • High channel density (12 channels on 5x5 mm2)

    • Low power (10 mW / channel)

    • Low cost (< 100$ / channel incl. VME board)

Dt

Dt

Dt

Dt

Dt

Fermilab


Folded layout

Linear inverter chain causes non-linearity

Folded Layout

Fermilab


Tail biting

“Tail Biting”

speed

enable

1

2

3

4

1

2

3

4

Fermilab


Sample readout

I

DRS2

DRS3

Sample readout

DRS1

Tiny signal

20 pF

0.2 pF

Temperature

Dependence

~kT

Fermilab


Tackling the search for lepton flavor violation with ghz waveform digitizing using the drs chip

DRS3

  • Fabricated in 0.25 mm 1P5M MMC process(UMC), 5 x 5 mm2, radiation hard

  • 12 ch. each 1024 bins,6 ch. 2048, …, 1 ch. 12288

  • Sampling speed 10 MHz … 5 GHz

  • Readout speed 33 MHz, multiplexedor in parallel

  • 50 prototypes receivedin July ‘06

Fermilab


Vme board

VME Board

40 MHz 12 bit FADC

USB adapter

board

32 channels input

General purpose VPC board built at PSI

Fermilab


Bandwidth linearity

Bandwidth + Linearity

  • Readout chain shows excellent linearity from 0.1V … 1.1V @ 33 MHz readout

  • Analog Bandwidth is currently limited by high resistance of on-chip signal bus, will be increased significantly with DRS4

0.5 mV max.

450 MHz (-3dB)

Fermilab


Signal to noise ratio

Signal-to-noise ratio

  • “Fixed pattern” offset error of 5 mV RMScan be reduced to 0.35 mV by offsetcorrection in FPGA

  • SNR:

  • 1 V linear range / 0.35 mV = 69 dB (11.5 bits)

Offset

Correction

Fermilab


12 bit resolution

12 bit resolution

<8 bits effective resolution

11.5 bits effective resolution

Fermilab


Sampling speed

Sampling speed

  • Unstabilized jitter: ~70ps / turn

  • Temperature coefficient: 500ps / ºC

  • How far wan we go?

  • 0.250 um technology: 8 GHz

  • 0.130 um technology: 15 GHz

~200 psec

Vspeed

PLL

Reference

Clock (1-4 MHz)

R. Paoletti, N. Turini, R. Pegna, MAGIC collaboration

Fermilab


Timing reference

Timing Reference

domino wave

signal

20 MHz

Reference clock

8 inputs

PMT hit

shift register

Domino stops after

trigger latency

Reference

clock

MUX

  • Calibrate inter-cell Dt’s for each chip

  • 200 ps uncertainty using PLL

  • 25 ps uncertainty for timing relative to edge

Fermilab


What timing can be obtained

What timing can be obtained?

  • Detailed studies by G. Varner1) for LAB3 chip

  • Bin-by-bin calibration using a 500 MHz sine wave

  • Accuracy after calibration: 20 ps

1ns

1) G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007)

Fermilab


On chip pll

On-chip PLL

Simulation:

loop filter

DRS4

Vspeed

PLL

Reference

Clock

fclk = fsamp / 2048

  • On-chip PLL should show smaller phase jitter

  • If <100ps, no clock calibration required

Fermilab


Comparison with other chips

Comparison with other chips

Fermilab


Waveform analysis

Waveform Analysis

What can we learn from acquired waveforms?


On line waveform display

On-line waveform display

S848

PMTs

“virtual oscilloscope”

template

fit

click

pedestal

histo

Fermilab


Qt algorithm

QT Algorithm

original

waveform

t

  • Inspired by H1 Fast Track Trigger (A. Schnöning, Desy & ETH)

  • Difference of Samples (= 1st derivation)

  • Hit region defined when DOS is above threshold

  • Integration of original signal in hit region

  • Pedestal evaluated in region before hit

  • Time interpolated using maximum value and two neighbor values in LUT  1ns resolution for 10ns sampling time

Region for pedestal evaluation

integration area

smoothed and

differentiated (Difference Of Samples)

Threshold in DOS

Fermilab


Pulse shape discrimination

Pulse shape discrimination

a

g

Leading edge Decay time AC-coupling Reflections

Fermilab


T distribution

t-distribution

ta = 21 ns

tg = 34 ns

Waveforms can be clearly distinguished

a

g

Fermilab


Coherent noise

Coherent noise

SiVi (t)

All PMTs

Pedestal

average

Charge

integration

  • Found some coherent low frequency (~MHz) noise

  • Energy resolution dramatically improved by properly subtracting the sinusoidal background

  • Usage of “dead” channels for baseline estimation

Fermilab


Pileup recognition

Pileup recognition

DT 8ns

DT 50ns

original

DT 10ns

DT 100ns

derivative

Dt = 15ns

E1

E2

MC simulation

DT 15ns

Rule of thumb: Pileup can be detected if DT ~ rise-time of signals

Fermilab


Crosstalk elimination

Crosstalk elimination

Crosstalk removal by subtracting empty channel

subtract

Hit

Hit

Fermilab


Spurious noise problem

Spurious Noise Problem

  • Found “sometimes” a high frequency“ring” on all channels

  • 40 MHz, ~20 mV, 1kHz repetition

  • Finally identified the liquid xenonpump as the source

  • This noise can screw up timingfor rare events

  • Without waveform digitizing, thiswould have been very hard todebug

Fermilab


Template fit

Template Fit

  • Determine “standard” PMT pulse by averaging over many events  “Template”

    • Find hit in waveform

    • Shift (“TDC”) and scale (“ADC”)template to hit

    • Minimize c2

    • Compare fit with waveform

    • Repeat if above threshold

  • Store ADC & TDC values

pb Experiment

500 MHz sampling

Fermilab


High pass filtering

High pass filtering

  • Get rid ofbaseline (lowfrequency)noise

  • Improveresolutionsignificantly

originalwaveform

template fit

integration

area

after optimized high pass FIR filter

Fermilab


Baseline subtraction

Baseline Subtraction

Baseline

Subtraction

100 MHz Clock

12 bit

Latch

Latch

Latch

Latch

Calibrated and linearized signal

Baseline

subtracted

signal

+

Latch

LUT

12x12

S

-

S

S

-

+

S

S

Latch

Baseline

Register

<thr

Fermilab


Constant fraction discr

Constant Fraction Discr.

Delayed

signal

Inverted

signal

Sum

Clock

12 bit

Latch

Latch

Latch

Latch

+

Latch

Latch

S

+

<0

&

MULT

0

Fermilab


Data reduction

Data Reduction

  • Zero suppression: hit if max. value > n x s(baseline)

  • Readout window: start / width in respect to trigger

  • Pile-up flag: Zero-crossings of first derivation

  • Re-binning 4:1, 8:1, 16:1

  • ADC: Numerical integral of hit over baseline

  • TDC: Only simple threshold (usable to recognize accidentals) and time-over-threshold

4 ns bins

0.5 ns bins

MEG: Applying to 94% of 100 Hz data

Keeping only 6 Hz of waveforms

TOT

Fermilab


Huffman encoding

0

10

1

110

11

111

S

16

20

Huffman encoding

0

0.6

1

1

0.2

-1

0.4

0.2

0.2

2

0

Fermilab


Where to perform waveform analysis

Where to perform waveform analysis?

  • Switching from ADC/TDC to ~GHz waveform digitization increases amount of data by ~1000x

  • Many algorithms suitable for on-board (FPGA) processing

    • Charge integration and time estimation (“QT”)

    • Zero-suppression, re-binning, Huffman encoding

    • Basic pile-up recognition (zero-crossings of derivative)

  • Algorithms for embedded CPUs or PC farms

    • Inter-channel cross-talk removal

    • Template fit (floating point)

FPGA

Front

End

PC

Off-line Analysis

DRS

Fermilab


Daq system principle

DAQ System Principle

Liquid Xenon Calorimeter

Timing Counter

Drift Chamber

Active Splitter

VME

VME

LVDS parallel bus

Trigger

Event number

Event type

Trigger

opticallink(SIS3100)

Waveform

Digitizing

Busy

Rack PC

Rack PC

GBit Ethernet

Rack PC

Rack PC

Switch

Rack PC

Rack PC

Rack PC

Rack PC

Rack PC

Event Builder

Fermilab


Multi threading model

Multi-threading model

Calibration

Thread

Zero-copy ring buffers

VME

Round-Robin

distribution

Calibration

Thread

VME

Transfer

Thread

Collector

Thread

Calibration

Thread

Network

Calibration

Thread

Fermilab


Optimal rate with 4 calibration threads

Optimal rate with 4 calibration threads

Fermilab


Daq system

DAQ System

  • Use waveform digitization (500 MHz/2 GHz) on all channels

  • Waveform pre-analysis directly in online cluster (zero suppression, calibration) using multi-threading

  • MIDAS DAQ Software

  • Data reduction: 900 MB/s  5 MB/s

  • Data amount: 100 TB/year

2000 channelswaveform digitizing

DAQ cluster

Fermilab


Advanced topics

Advanced Topics

Reduced dead time, integrated triggering


Residual charge problem

Solution: Clear before write

write

clear

“Residual charge” problem

R

After sampling a pulse, some residual charge remains in the capacitors on the next turn and can mimic wrong pulses

Implemented

in DRS4

“Ghost pulse”

2% @ 2 GHz

Fermilab


Roi readout mode

ROI readout mode

delayed trigger stop

normal trigger stop after latency

stop

Trigger

Delay

33 MHz

e.g. 100 samples @ 33 MHz  3 us dead time(2.5 ns / sample @ 12 channels)

readout shift register

Patent pending!

Fermilab


Daisy chaining of channels

1

1

0

0

1

0

0

0

0

1

0

0

1

0

0

0

Daisy-chaining of channels

Domino Wave Generation

1

Channel 0 – 1024 cells

0

Channel 1 – 1024 cells

1

Channel 2 – 1024 cells

0

Channel 3 – 1024 cells

1

Channel 4 – 1024 cells

0

Channel 5 – 1024 cells

1

Channel 6 – 1024 cells

0

Channel 7 – 1024 cells

DRS4 can be partitioned in: 8x1024, 4x2048, 2x4096, 1x8192 cells

Fermilab


Interleaved sampling

G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007)

Interleaved sampling

5 GSPS * 8 = 40 GSPS

delays (200ps/8 = 25ps)

Fermilab


Almost dead time free system

“Almost” Dead time free system

VME board

16 channel

CMC1

32 channel

MUX

CMC2

One board is active while other board is read out

Fermilab


Drs4 packaging

DRS4 packaging

DRS4

flip-chip

DRS4

DRS3

5 mm

9 mm

18 mm

Fermilab


New generation of fadcs

New generation of FADCs

  • 8 simultaneous flash ADCs on one chip

  • Requiredifferentialinput

  • DRS4 has beenredesigned withdifferentialoutput

Fermilab


Trigger an daq on same board

DRS4

MUX

Trigger an DAQ on same board

  • Using a multiplexer, input signals can simultaneously digitized at 65 MHz and sampled in the DRS

  • FPGA can make local trigger(or global one) and stop DRSupon a trigger

  • DRS readout (5 GHz samples)though same 8-channel FADCs

  • Multiplexer will be included in DRS4

global trigger bus

trigger

FPGA

DRS

FADC12 bit

65 MHz

analog front end

LVDS

SRAM

No splitter (signal quality!), no dedicated trigger boards, no dedicated scalers

Fermilab


Redefinition of daq

TDC

Disc.

Scaler

ADC

Scope

“Redefinition of DAQ”

Because of the high channel density of the DRS system, it becomes affordable to use waveform digitizing in experiments which today use ADC/TCDs

DRS

~GHz

~100

MHz

FADC

FPGA

CPU

Fermilab


Availability

32-channel 65 MHz/12bit digitizer

“boosted” by DRS4 chip to 5 GHz

Availability

  • DRS4 will become available in larger quantities in summer ’08

  • Chip can be obtained from PSI on a “non-profit” basis

    • Delivery “as-is”

    • Reference design (schematics) from PSI

    • Costs ~ 10-15$/channel

    • Costs decrease if we find sell more…

  • Full VME board can be purchased from CAENprobably end of ’08 with firmware forpeak sensing ADC, QDC, …

  • Struck, others, … ?

Fermilab


Other experiments using drs

Other experiments using DRS

BPM for [email protected]

Magic Telescope, Canary Islands

8 chn.with

PGA

PET scanners

MACE TelescopeIndia

Fermilab


Conclusions

Conclusions

  • Switched Capacitor Array techniques has prospects to trigger a quantum step in data acquisition

  • The DRS chip has been designed with maximum flexibility and can therefore be used in many applications

  • Collaboration on a scientific basis is very welcome

Datasheets, publications:

http://midas.psi.ch/drs

Fermilab


  • Login