KPiX & EMCal

1. KPiX & EMCal • SLAC • D. Freytag • G. Haller • R. Herbst • T. Nelson • mb • Oregon • J. Brau • R. Frey • D. Strom • BNL • V. Radeka • UC Davis • R. Lander • M. Trapanni SLAC DOE Review M. Breidenbach

2. SiD Calorimetry • Significant component of the motivation for the SiD strategic design is excellent jet energy resolution – within rational and constrained cost. • Proposed solution is an imaging calorimeter optimized for particle flow analysis. SLAC DOE Review M. Breidenbach

3. K0L n After removing charged tracks and associated calorimeter hits After removing photons SLAC DOE Review M. Breidenbach

4. SiD EMCal Issues • High spatial segmentation • Pixellate large area Si detectors that can tile surface. • Closely couple readout electronics to maximize performance, minimize cables. • Minimize transverse shower spread – small Moliere radius • Tungsten radiator • Minimal gap – 1 mm seems ok but certainly challenging. • High temporal segmentation • Minimize confusion by tagging hits with bunch crossing • Measure several hits per train • Manage thermal issues from the beginning • Take full advantage of ILC duty cycle (1 ms train, 199 ms off) to minimize average power. • Transfer that heat to radiator material and remove on edge, avoiding separate conduction layers or fluid flow in stack. SLAC DOE Review M. Breidenbach

5. R 1.27 m CAD overview SiD ECAL overview • 20 layers x 2.5 mm thick W • 10 layers x 5 mm thick W • ~ 1mm Si detector gaps • Preserve Tungsten RM eff= 12mm • Highly segmented Si pads 12 mm2 SLAC DOE Review M. Breidenbach

6. Conceptual design SLAC/ Annecy • Very aggressive mechanical and electronics integration is needed to preserve the Moliere radius W plate ~ 200 Kg Module ~7000 Kg • W plates joined by ‘rods’ • Wafers ‘on’ W • ReadOut chips on wafers FEA analysis is in progress SLAC DOE Review M. Breidenbach

7. Wafer and readout chip connections SLAC DOE Review M. Breidenbach

8. Detector Layout Real Thing SLAC DOE Review M. Breidenbach

9. SLAC DOE Review M. Breidenbach

10. Si Detector, version 2 design • Accommodate mechanical structure. • Topside bias connection • Improve trace design • 1024 pixels SLAC DOE Review M. Breidenbach

11. KPiX Overview • SLAC/Oregon/BNL is developing a read out chip (ROC) motivated by the Si-W calorimeter. • Highly integrated into structural design – bump bonded to detector • 1024 pixels / ROC ---Thus working name KPiX • Rough concept for “DAQ” strategy. • Identical architecture should work for Si strips. (A reduced dynamic range 2048 pixel chip was considered and dropped in favor of one development project) • Identical architecture should work for HCal and muon system (features added to baseline for input signal polarity inversion). • Beginning architectural integration in detector. • Will not work for very forward systems. SLAC DOE Review M. Breidenbach

12. “Longitudinal” Data Cable “Transverse” Data Cable Data Concentrator Conceptual Schematic – Not to any scale!!! Locating Pins Readout Chip “KPix” Detectors Tungsten Radiator ~ 1m SLAC DOE Review M. Breidenbach

13. Tungsten Tungsten EMCal Schematic Cross section Metallization on detector from KPix to cable Bump Bonds Kapton Data Cable KPix Si Detector Kapton Heat Flow Thermal conduction adhesive SLAC DOE Review M. Breidenbach

14. Charge Amplifier Event discriminator implemented as limiter followed by discriminator. Limiter holds off resets, permitting longer integration time for discriminator and data hold. Discriminator threshold selected from either of two ROC wide DAC’s. Track & Hold (x4) Cal strobe gated by 1024 long SR. Pixel pattern arbitrary. SLAC DOE Review M. Breidenbach

15. Electronics requirements • Signals • <2000 e noise • Require MIPs with S/N > 7 • Max. signal 2500 MIPs (5mm pixels) • Capacitance • Pixels: 5.7 pF • Traces: ~0.8 pF per pixel crossing • Crosstalk: 0.8 pF/Gain x Cin < 1% • Resistance • 300 ohm max • Power • < 40 mW/wafer  power cycling (An important LC feature!) • Provide fully digitized outputs of charge and time on one ASIC for every wafer. SLAC DOE Review M. Breidenbach

16. Pulse “Shaping” • Take full advantage of synchronous bunch structure: • Reset (clamp) feedback cap before bunch arrival. This is equivalent to double correlated sampling, except that the “before” measurement is forced to zero. This takes out low frequency noise and any integrated excursions of the amplifier. • Integration time constant will be 0.5 – 1 μsec. Sample synchronously at 2 – 3 integration time constants. • Time from reset 1 – 3 μsec, which is equivalent to a 1 – 3 μsec differentiation. • Noise: ~1000 e- for ~ 20 pF. (100 μA through input FET). SLAC DOE Review M. Breidenbach

17. Power SLAC DOE Review M. Breidenbach

18. KPiX SiD Readout Chip Prototype 2 now being tested at SLAC. One cell. Dual range, time measuring, 13 bit, quad buffered Prototype: 2x32 cells: full: 32x32 SLAC DOE Review M. Breidenbach

19. SLAC DOE Review M. Breidenbach

20. Data Flow - ~ 4 Mb/train from backgrounds… SLAC DOE Review M. Breidenbach

21. Comments • The basic KPiX architecture should work with all the low occupancy sub-systems- • Including Tracker, EmCal, HCal, and muon system. • It (probably) does not address VXD issues – presumably CMOS to be developed – or the completely occupied Very Forward Calorimeters. • A variant might work in the forward regions of the tracker and calorimeters. • The architecture is insensitive to the bunch separation within a train. • The cost of a mask set is high, so development will be with 2 x 32 subsets instead of the 32 x 32 array. • The unit cost of a large number of chips seems fine - <~ $40. • Substantial design and simulation is done on KPiX Readout chip. • KPiX3 ~ready to go, but will await testing of KPiX2 which came back last week. SLAC DOE Review M. Breidenbach