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Progress on STS CSA chip development. E. Atkin Department of Electronics, MEPhI A.Voronin SINP, MSU. Main research goals. Design and production (via MPW) of a test purpose chip for SST prototyping Lab tests of ICs manufactured. Study of 0.18 µ UMC process features

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Progress on sts csa chip development

Progress on STS CSA chip development

E. Atkin

Department of Electronics, MEPhI

A.Voronin

SINP, MSU


Main research goals
Main research goals

  • Design and production (via MPW) of a test purpose chip for SST prototyping

  • Lab tests of ICs manufactured. Study of 0.18µ UMC process features

  • Study of a face-to-face interface to Si strip prototype

  • IC radiation hardness tests technique development

Feb 28 - Mar 3, 2006 CBM meeting at GSI


Csa schematic
CSA schematic

  • CSA is based on folded cascode architecture

  • DC and AC input coupling are available

  • Two mirrored versions of CSA has been studied. These are:1) version with PMOS input transistor and2) one with NMOS transistor. In accordance to the foundary Design Kit models at reasonable shaping the PMOS version showed a greater noise performance and was selected for the input device of CSA

  • Input PMOS: 0.5 mA (half power budget), 1.2mm*0.18um

  • Feedback cap 2pF sets the gain to 0.5 mV/fC. Feedback is optimized for up to 100pF capacitive detectors (pads, strips and so on)

  • Noise at CSA output (wide bandwidth) at 100 pF of Cdet: 200 uV rms for CSA core only, 350 uV rms for CSA with active feedback

  • Maximal signal at 5% non-linearity – 0.5 V (at ±1V supply and Cdet up to 100 pF)

  • Supply voltages: 1) 0 and +1.8V or 2) -0.9 and +0.9 V

  • 1.0 mW/channel

Feb 28 - Mar 3, 2006 CBM meeting at GSI


Csa core
CSA core

1.2mm*0.18µm0.5 mA

Feb 28 - Mar 3, 2006 CBM meeting at GSI


Csa simplified structure
CSA simplified structure

CSA core

Non-linear active feedback (leakage current compensation) – 1.0 uA max

Biasing block

Feb 28 - Mar 3, 2006 CBM meeting at GSI


Channel pins for csa
Channel pins for CSA

  • Input

  • Output

  • Monitoring of leakage current

  • Vdd, Vss + input transistor reference (AGND)

Feb 28 - Mar 3, 2006 CBM meeting at GSI


Rail to rail op amp
Rail-to-rail Op amp

  • Features:

  • Universal block for shapers, buffer stages

  • Fast (few ns rise time) and low power (less than 1 mW)

Feb 28 - Mar 3, 2006 CBM meeting at GSI


Layout

(Pad restrictive design)

Layout

60 pads, 1.5*1.5 sq.mm

2 full-time engineers + 4 diploma students, half a year for design

Structure blocks: 8 CSAs, test purpose CSA core, rail-to-rail opamp, clocked comparator

test CSA core

8 CSAs

opamp

comp

To be realized in a 0.18 um, single poly, six metal, salicide CMOS process from UMC, Taiwan.

That is a mini-ASIC run, scheduled via Europractice

Feb 28 - Mar 3, 2006 CBM meeting at GSI


This talk covers partially the efforts on …

  • Development of building blocks for data-driven architecture, according to UMC CMOS 0.18 µm. These blocks are:

    • Preamp

    • Amplitude (slow) antialiasing and dynamic range saving shaper

    • Timing (fast), hit defining shaper

    • Low offset high-speed comparator both for hit finder and ADC. Studying both clocked and non-clocked options

    • Threshold DAC (6-8 bit)

    • Fast low-bit (4…6 or 8 bit ?) ADC

    • Analog Derandomizer (deadtime free analog unit with n-inputs and m-outputs, n>m)

    • Rail-to-rail op amp (high speed buffer)

      Common issues are: low power consumption, reasonable speed & chip area

Feb 28 - Mar 3, 2006 CBM meeting at GSI



Remarks
Remarks GSI

  • This prototype ASIC blocks focus on study of possibilities and merits of UMC 0.18um process

  • All 8 CSAs are different each other. It is needed to optimize the structure and biasing of CSA

  • Additional information is in:CBM-STS-note-internal-2006-001 of 10 Jan 2006The metadata URL is http://www.gsi.de/documents/DOC-2006-Jan-20_e.html

Feb 28 - Mar 3, 2006 CBM meeting at GSI


Participants: GSIMSU – schematics, board designs, test stations, testingMEPhI – schematics, layout, verification, GDSII files, ASIC test station, ASIC testing

Feb 28 - Mar 3, 2006 CBM meeting at GSI


Test board
Test GSIboard

Feb 28 - Mar 3, 2006 CBM meeting at GSI


Test board features
Test GSIboard features

  • Adjustable voltage regulators 0.9V and 3.3V

  • Calibration capacitors

  • Detector capacitor equivalents

  • Line driver Cin = 2 pF

  • Voltage and current bias components

  • Offset regulators

  • Output loads

  • Low level clock drivers

  • All components are installed onto sockets

Feb 28 - Mar 3, 2006 CBM meeting at GSI


Test status the main csas in one chip have been checked only
Test status GSI(the main CSAs in one chip have been checked only!)

  • Powerless DC tests for shorts, openings and passive resistivity  OK

  • DC tests at nominal bias conditions  not passed

  • Dynamic tests  not performed

Feb 28 - Mar 3, 2006 CBM meeting at GSI


Chip interconnection
Chip interconnection GSI

  • Full height is 1.6 mm

  • Microconnector pitch 0.3 mm

  • Chip VA-1, 128 channels, 50 µm input pitch, 6*4 mm

  • Flexible interconnection PCB, 70 µm

  • Chip connection type – bonding

Feb 28 - Mar 3, 2006 CBM meeting at GSI


Summary
Summary GSI

  • Presented are the main simulation results of CSA chip design, given as a part of the CBM MPW join run (UMC 0.18 um CMOS, June 2005, mini-ASIC conditions)

  • Tests for 8-ch CSA appear to be more negative than positive, but should be continued with more than one chip sample

  • Tests of the rest blocks in chip (ver.2 CSA, opamp, comp) should be performed too

Feb 28 - Mar 3, 2006 CBM meeting at GSI


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