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Principle of ATM （3）

Principle of ATM （3）. 11. ATM Switch Architecture. 1 . The Basic Concept of the ATM Switches The basic switching node comprises a set of interfaces for input and output connections, a switching fabric and a set of software functions.

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Principle of ATM （3）

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  1. Principle of ATM （3） SCUT DT&P Labs

  2. 11. ATM Switch Architecture SCUT DT&P Labs

  3. 1. The Basic Concept of the ATM Switches • The basic switching node comprises a set of interfaces for input and output connections, a switching fabric and a set of software functions. • The interface cards contain a buffer for input and output traffic. This buffer acts as a scheduler that selects which cells are to be placed upon the output media. • The fabric is the high-speed component that moves cells from input buffer to output buffer. SCUT DT&P Labs

  4. 1. The Basic Concept of the ATM Switches (cont.) • Software entities include the signalling stack. The signalling stack includes functions to handle signalling across the UNI and the NNI (for public or private internal inter-node signalling). • Management software is also located here: ILMI(Interim Local Management Interface), configuration software and MIB structures. SCUT DT&P Labs

  5. Management software Signalling software Interfaces Fabric Input/output buffers scheduler, mappings High-speed switching ATM Switching Nodes SCUT DT&P Labs

  6. 2. ATM Switch Fabric Architectures • The actual structure of the fabric is still the subject of intense research. There are, however, several 'classic' designs worth mentioning. SCUT DT&P Labs

  7. Arbiter 2. ATM Switch Fabric Architectures (cont.) (1) Shared bus A shared bus architecture provides a high-speed bus with an arbitration mechanism. All traffic shares a single bus. As such, the bus is an obvious bottleneck. This design has been successfully used in practice, but modern switches tend not to use this design. Shared bus SCUT DT&P Labs

  8. 2. ATM Switch Fabric Architectures (cont.) (2) Crosspoint The crosspoint is also a widely used design. Again, the theory of crosspoints was well defined before the advent of ATM. The architecture does not scale well (the number of crosspoints grows exponentially with the number of inputs). We find this design in small to medium switches. Crosspoint SCUT DT&P Labs

  9. Queues Queues Queues 2. ATM Switch Fabric Architectures (cont.) (3) Shared memory Shared memory is well defined and widely implemented as a fabric design. The design allows the easy segregation of different traffic classes. As the memory grows, however, control grows in complexity and at about 65 thousand cells of storage, there is a need to move from 16-bit to 32-bit processing. The design works well and is found in small to medium switches. Shared memory SCUT DT&P Labs

  10. 2. ATM Switch Fabric Architectures (cont.) (3) Delta Large-scale design moves into parallel paths and internal paths that are not shared. The generic name for these fabrics is Delta. As a cell propagates across the fabric its destination (output port) is defined in small incremental steps. In this configuration 'self-routing' fabrics emerge in cases where the cell finds its own way to the output port. Delta SCUT DT&P Labs

  11. 3. Buffers and Buffering • Buffering can occur at the input, at the output and inside the fabric. • Input buffers tend to be small as the rate at which traffic arrives is entirely defined by the rate of the interface (line rate). • Output buffers need to be larger as several inputs could be simultaneously directing cells to a single output (n x 155 does not fit into 155). SCUT DT&P Labs

  12. Input Buffer Input Buffer Input Buffer Output Buffer Output Buffer Output Buffer Buffers and Buffering Interfaces F A B R I C Input Buffer Output Buffer Input/output buffers scheduler, mappings SCUT DT&P Labs

  13. 3. Buffers and Buffering (cont.) Output buffering may be implemented as part of the shared memory architecture where several queues can be created, one for each service category. With several queues, preference can be given to the CBR queue over the VBR queue. In extreme cases, we can provide one queue per connection and implement a very refined prioritisation scheme. SCUT DT&P Labs

  14. 5. Blocking Problems • Head-of-Line Blocking (HOL) • HOL blocking can occur when high-priority traffic is introduced to a queue that already contains traffic of a lower priority. In this case the high-priority traffic has to wait. • Given that the high-priority traffic (for instance, voice traffic) may be delay-sensitive, this could be a problem. • A better solution is to use several queues with one queue per service category or one queue per connection, although this is expensive. SCUT DT&P Labs

  15. 6. Blocking Problems (cont.) An output interface includes some form of scheduling process. The scheduler preferentially takes cells from high-priority (low-delay) queues. This means that CBR can get preference over VBR/ABR/UBR etc. SERVER QUEUE SCUT DT&P Labs

  16. 5. Blocking Problems (cont.) (2) Blocking in the Fabric Blocking can occur in the fabric (in all architectures) when a resource that is in use internally is required by another cell. The most obvious case would be a shared bus where everything has to wait for the current cell to transmit the bus before anything else happens. SCUT DT&P Labs

  17. 5. Blocking Problems (cont.) (2) Blocking in the Fabric In a delta switch, two cells may be contending for the same output of a switching element. All designs minimise the probability of blocking. Element in the fabric SCUT DT&P Labs

  18. 5. Blocking Problems (cont.) The easiest way to solve the problem is to increase the fabric speed. If the switch has 32 ports all rated at 155 Mbit/s, then a shared memory with a throughput of 5 Gbit/s (32 x 155 m) is able to handle the simultaneous arrival of a cell at each input. The another way to solve the problem is to increase the width of fabric bus to depress the requirement of the fabric speed. SCUT DT&P Labs

  19. 12. Building ATM Networks SCUT DT&P Labs

  20. 1. The Carrier Network • The hierarchy created by two levels of multiplexing (path and channel) is utilized by the carrier to create a scaleable network. • This scalability simplifies setting up connections and overall manageability. • At the core of the network we find VP crossconnects. These are high-capacity,high-performance switches connected by SONET/SDH rings with protection. • The structure of this network component changes slowly. SCUT DT&P Labs

  21. Access VP/VC Switching Edge Devices Core/Backbone UNI UNI UNI UNI VP Crossconnect FRAME RELAY Edge Devices UNI Edge Devices PBX PBX The Carrier Network (PBX:private branch (telephone) exchange:专用分组交换机) SCUT DT&P Labs

  22. 1. The Carrier Network （cont.） Surrounding the core is a 'cloud' of access switches that perform VC switching. Ideally, these VC switches are fully meshed. When a connection needs to be established, it is only necessary to select available channels on already established paths. From this access cloud the UNI can be used to connect to customer premises, which may either be simple end-stations or connection points to a private network. SCUT DT&P Labs

  23. 2. Campus ATM Network • The diagram on the next page shows a campus network with an ATM backbone. An important point to note here is that the network is not end-to-end ATM. • Rather an existing LAN technology, for example Ethernet, is used to connect PCs. • Voice traffic may be carried across the ATM backbone, however it may well be more economically favourable to directly interconnect the PBXs. SCUT DT&P Labs

  24. 2. Campus ATM Network (cont.) SCUT DT&P Labs

  25. 2. Campus ATM Network (cont.) • If the offices were geographically relocated, thus necessitating WAN links, a stronger business case may then exist to trunk voice over ATM. • In the diagram on the last page note that there is redundant links from each router to the ATM network. SCUT DT&P Labs

  26. 2. End-to-end ATM network • For end workstations such as PCs to connect directly into the ATM network they must be equipped with ATM network interface cards (NICs). • For the PBX (private branch (telephone) exchange:专用分组交换机) to connect into the ATM network either the PBX will have an ATM interface card, or the ATM switch that the PBX is connected to must have either an E1 interface or circuit emulation interface cards installed. SCUT DT&P Labs

  27. 2. End-to-end ATM network (cont.) • The private network can be quite complex in its own right, with PNNI deployed across a campus or manufacturing plant. • This may be further refined closer to the desktop through low performance workgroup switches, and at the individual desktop where the workstation is equipped with an ATM NIC card. • An end-to-end ATM network would be expensive in comparison with traditional technologies such as Ethernet. However if the network has a high volume of traffic with many mission critical QoS requirements then such a network may be desirable. SCUT DT&P Labs

  28. Carrier Network UNI Catalyst 5000 PBX 2. End to end ATM Network ATMNIC Cards Workgroup Switch Campus Switch PNNI PBX E1 Enterprise Switch SCUT DT&P Labs

  29. 12. Circuit Emulation SCUT DT&P Labs

  30. 1. Circuit Emulation • The Circuit Emulation (CE) function enables existing TDM circuits to be mapped over ATM. • CE thus enables us to migrate an existing TDM network to ATM whilst preserving the investment in TDM equipment. • It is possible for the PBX (or similar TDM equipment) to have an ATM interface board. In this case the CE function is performed on the PBX which sends out ATM cells directly. • CE is broken into two versions: • structured • Unstructured. • All versions of CE use AAL1 CBR connections. SCUT DT&P Labs

  31. PBX PBX 1. Circuit Emulation ATM Network E1 E1 Circuit Emulated E1 CBR connection SCUT DT&P Labs

  32. 2. Unstructured Circuit Emulation In unstructured CE, the network does not attempt to recognize the internal circuit structure. Rather it simply transmits the entire circuit across the network. E1/T1 ‘pipe’ : 2/1.54 Mbps in 2/1.54 Mbps out. No recognition of circuit’s framing structure. SCUT DT&P Labs

  33. 2. Unstructured Circuit Emulation (cont.) E1 frame 32x8 bits = 256 bits 31 0 256 bits 376 bits = 47 bytes 376 bits = 47 bytes 1 byte AAL 1 header 53 bytes 48 bytes ATM cell header SCUT DT&P Labs

  34. 2. Unstructured Circuit Emulation (cont.) As can be seen from the diagram on last slide, a 376 bit (or 47-byte) chunk of the E1 source signal is taken. This 47 bytes have the AAL1 one-byte header added to make up the full 48-byte payload. You may wish to review the chapter on AAL 1. An ATM cell header is added, making a full ATM cell. These cells are then sent on a CBR connection. SCUT DT&P Labs

  35. 3. Structured Circuit Emulation Structured CE recognizes timeslots within the circuit to be emulated. An example of structured CE is given on next slide. In this example a single timeslot is extracted from the source E1 and mapped to an ATM cell. This means that particular timeslots may be mapped to different virtual circuits and hence to different destinations. Several timeslots from a source circuit may be mapped to one virtual circuit. This scenario is illustrated on the next slide. SCUT DT&P Labs

  36. 3. Structured Circuit Emulation (Example 1) 31 31 31 2 2 2 3 1 0 3 1 0 3 1 0 E1 frame n+1 E1 frame n+2 E1 frame n May need to pad out cell Problem - to fill cell payload requires us to wait for 47 samples: Trade off between efficiency and latency 47 bytes 1 byte AAL 1 header ATM cell header 53 bytes E1 frame 32x8 bits = 256 bits SCUT DT&P Labs

  37. 3. Structured Circuit Emulation (cont.) Recall that an E1 contains 32 timeslots per frame and that the first timeslot, timeslot 0, is used for framing. As framing is irrelevant within the ATM network this timeslot (timeslot 0) is often terminated within the first ATM switch and regenerated at the destination ATM switch which produces an E1 output. An AAL1 one-byte header will be included in each cell payload, thus to use the ATM bandwidth as efficiently as possible we should wait for 47 timeslots. In this case the application is voice traffic which is extremely delay-sensitive. SCUT DT&P Labs

  38. 3. Structured Circuit Emulation (cont.) Within structured CE it is possible to map several timeslots to one cell or VC. This is shown on the next slide. The diagram opposite displays an example of structured CE where more than one timeslot is mapped to an ATM cell. In this case timeslots 1, 3 and 6 are mapped to the same cell stream. The CSI bit in the even numbered AAL 1 headers is used to indicate that structured CE is being used. SCUT DT&P Labs

  39. 31 31 31 2 2 2 3 3 3 1 1 1 0 0 0 6 6 6 5 5 5 4 4 4 7 7 7 3. Structured Circuit Emulation (Example 2) E1 frame 32x8 bits = 256 bits E1 frame n+1 E1 frame n+2 E1 frame n May need to pad out cell Structured CE enables switching on a sub-2 Mbps level 47 bytes 1 byte AAL 1 header ATM cell header 53 bytes SCUT DT&P Labs

  40. 4. AAL1 - Time Stamp Clocking The Synchronous Residual Time Stamp Clocking (SRTS) method of clock information transfer is used to convey information from one end of the connection to the other. For this method to work, it is a requirement that the same derived network clock is available at both ends. The clock received at the interface is compared to the common reference clock (i.e. Stratum 1) and the difference is transmitted as a time stamp to the other end of the connection. The difference is then added to or subtracted from the common reference clock to regenerate the original clock frequency. SCUT DT&P Labs

  41. Synchronous Residual Time Stamp Clocking CSI bit in odd number cells contains the 4-bit time stamp. The mechanism relies upon a single system clock. Incoming cells CBR output Receive FIFO Strip time stamp Bit-rate clock is locked to sender’s clock Received SDUs Time stamps Local clock Adjust clock PLL PLL - Phase Locked Loop SDU - Service Data Unit FIFO - First In First Out SCUT DT&P Labs

  42. 4. AAL1 - Time Stamp Clocking (cont.) The Residual Time Stamp is actually a four-bit pattern transmitted by using the CSI bit of the SAR-PDU header when the sequence count value is 1,3,5 or 7. The whole technique is referred to as Synchronous Residual Time Stamp (SRTS). The timestamp is the value contained in the counter being driven by the network clock. The four low-order bits of the timestamp are called the residual part. Mathematically it can be demonstrated that four bits are sufficient to carry the synchronizing information across a global scale deployment. SCUT DT&P Labs

  43. 5. AAL1 - Adaptive Clock Recovery The fill level of the buffer is then used to control the frequency of the local clock. * If the buffer starts to empty, the clock is running too fast, and a phase lock loop mechanism is used to slow the clock down until the buffer returns to its mid-point. * If the buffer starts to fill then the clock is speeded up. As cells arrive at the switch, the sequence number is checked. If a cell is missing, a dummy is inserted into the buffer to maintain the timing integrity. The effect may be a short burst of noise, but the synchronization is kept, and the call will not be lost. SCUT DT&P Labs

  44. Local bit-rate clock +ve - ve Received SDUs Constant bit- rate output Dummy SDU Timing Point If FIFO fills faster than it empties: increase clock rate If FIFO empties faster than it fills: decrease clock rate If FIFO empties too fast inject dummy SDU to return to the timing point AAL1 - Adaptive Clock Recovery SCUT DT&P Labs

  45. 6. Adaptive Vs SRTS The SRTS method is appropriate for high-speed traffic, for example, E1 or DS (T1), where it takes a relatively short time to assemble 8 cells' worth of traffic. For slow-rate traffic however, the delay caused by waiting for 47 x 8 octets (8 cells) may be unacceptable. For these slower-rate traffic sources the adaptive scheme is more suitable, as a cell can be sent as soon as it is full. SCUT DT&P Labs

  46. 12. Classical IP over ATM SCUT DT&P Labs

  47. 1. Why Use IP over ATM? • Why IP? IP is the dominant global data communications standard. • Why ATM? ATM natively supports a specific Quality of Service. ATM is defined and available at higher speeds than competing technologies. ATM is currently the enabling technology for the Internet. • IP over ATM is an established and proven combination. The question is to find the best method of running IP over ATM. • IP over ATM enables the use of low cost equipment which provides very high speed forwarding SCUT DT&P Labs

  48. 2. Running IP over ATM - the Issues • IP is a network layer protocol, that is, it can’t be run ‘on the wire’. It has to be run ‘over’ something, in this case, ATM. In the LAN, IP is usually run over Ethernet. • IP is connectionless, ATM is connection-orientated. Accordingly, ATM uses signalling protocols to set up connections. Being connectionless, IP has no need for signalling. • Both IP and ATM have routing protocols, and they are are incompatible. • IP and ATM use different addressing schemes. SCUT DT&P Labs

  49. 3. QoS Considerations • ATM service categories - CBR, rt-VBR, nrt-VBR, ABR, UBR, GFR • How do we map from IP? • – IP is a best effort protocol • – ToS field in IP header unused • Traffic coming off LAN? • No method within Ethernet to define QoS SCUT DT&P Labs

  50. 4. Standards Bodies • （1）IP - Internet Engineering Task Force (IETF) (www.ietf.org) • （2）ATM - ATM Forum • IETF responsible for: • – Encapsulation • – Classical IP • – Multicast Address Resolution Server (MARS) • – Multi protocol Label Switching (MPLS) • ATM Forum responsible for: • – LAN Emulation (LANE) • – Multiprotocol over ATM (MPOA) SCUT DT&P Labs

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