I. Introduction. Figure 2 CG stage at high frequencies The trans-impedance gain calculation is as follow:
Figure 2 CG stage at high frequencies
The trans-impedance gain calculation is as follow:
For s = 0, Vout / Iin = RD. In the typical design, the input pole, (gm1+gmb1)/Cin, may be closer to the origin compared to the output pole, 1/(RDCout), because the photodiode capacitance is quite large (in the range of 100 to 500 fF).
The calculation of the total output noise voltage and the total input-referred noise current:
This result can be interpreted as the noise of M1 integrated across a bandwidth of ωp,out/4 plus the noise of M2 integrated across a bandwidth of ωp,in/2.
The noise contributed by M1 directly scales with Cin and the frequency. The noise contributed by RD to the input also rises as |Cins| becomes comparable with gm1+gmb1.
If RD is decreased to accommodate a greater bias current, then its noise current increase and the trans-impedance gain falls. If M2 is made wider to allow a smaller VDS2, both its noise current and drain capacitance increase.
Low-Noise Trans-impedance Amplifiers (TIAs) for Communication SystemJie Zou Faculty Advisor: Dr. Kamran Entesari, Graduate Advisor: Sarmad Musa Department of Electrical and Computer Engineering at Texas A&M University
III.Case Study for Open-loop stage TIAs
Figure 4 Small Signal Frequency Response
Figure 6 Effect of R0 Component for Transimpedance Gain
Department of Electrical and Computer Engineering
Texas A&M University
College Station, TX 77843-3128
Figure 3 Schematic of A Open-loop Stage TIA
Figure 5 Small Signal Frequency Response (No Gain Boosting)
Figure 7 Effect of C0 Component for Transimpedance Gain
Table 1 Performance Summary
This paper analyzes the trans-impedance gain, bandwidth, and noise performance of open-loop stage TIAs, and discusses the trade-offs noise, bandwidth, gain, and supply voltage.
In the case study for open-loop stage trans-impedance amplifier, the example circuit can have a very high 72.354dB Ω gain and a low 122.7nA total input RMS referred noise, but it has a very narrow bandwidth of only 337.34M Hz. Thus, It needs further research on the bandwidth of TIAs and the improvement designs for the buffer stage of TIAs.
From the Table 1, we can observe that the TIA with the gain boosting improvement technique has a higher trans-impedance gain and much less total input referred RMS noise than the one without current mirror. The biggest advantage of gain boosting technique can increase M0 DC current a lot without causing the voltage headroom problem. If ID0 increases, the value of gm + gmb increases a lot, so the input noise current decreases, but the bandwidth would be limited.
From the Table 2, we can see that the device of PMOS0 and PMOS1 contribute 76.57% of total noise, because the drain-bulk and drain-gate capacitances of M4 may substantially increase the time constant at the node of drain of M4, which is caused by the reason that the PMOS transistor suffers from low mobility and must therefore be quite wide to carry a large current with a reasonable drain-source voltage.
II. Topology of Open-Loop Stage Amplifiers
For a given photodiode capacitance, the bandwidth of TIA is maximized by minimizing the input resistance of circuit.
Thus, the circuit should be able to provide both a low input resistance and a high gain. An amplifier stage exhibits a low impedance is the common-gate (CG) (for field device) or common-base (CB) (for bipolar devices) topologies.
Let us discuss the common-gate stage topology at high frequencies, base on the Figure 2.
Table 2 Noise Distribution
 B. Razavi, Design of Integrated Circuit for Optical Communications, McGraw-Hill, 2003
Undergraduate Summer Research Grant Program