Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design

1. Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Course and contest Results of Phase 3 EikeSchweißguth Institute MD, University of Rostock

2. Recap Partial Products RC Adder Register RC Adder Register Previous Coefficient Register RC Adder

3. Multiplier with Carry Save Adders Partial Products CS Adder CS Adder Register Previous Coefficient Pipelined RC Adder CS Adder Register Register Register CS Adder

4. Adder • RC Adder with 4 pipeline stages • only one adder  adder architecture does not affect metric a lot • minor improvement possible by using more efficient adder architecture

5. Coefficients & Pipelining • total number of pipeline stages: 6 • coefficients optimized to keep the filter response as close as possible to the reference design while producing a maximum of 3 partial products • reduced overall adder width because the last 16 bits are cut off at the output anyway

6. Tool Optimization – Frequency • max_dynamic_power negative effect • max_leakage_power negative effect • frequency: • tool automatically optimizes the design to meet the clock constraint • e.g. testing of different logic implementations, transistor upsizing, logic splitting

7. Tool Optimization – Frequency • far away from the limits of the logic implementation: dynamic power increases nearly linearily with the frequency, leakage power is nearly constant • leakage power and dynamic power increase significantly when reaching the limits of the design  “sweet spot” has to be found Metric [GHz/(mW*µW)] f [GHz]

8. Tool Optimization – Library Selection • LVT Library: • HVT Library: • SVT Library: • useful for achieving high frequencies • more than 2 GHz possible with the current design • bad metric due to power consumption (high leakage power) • significantly lower leakage power • still high frequency possible • best metric • tradeoff between leakage power and frequency

9. Metric

10. Frequency Response

11. Thank you for your attention!