IL2207 SoC Architecture Course Jan – March 2012, KTH

1. IL2207SoC Architecture CourseJan – March 2012, KTH Zhonghai Lu, Axel Jantsch

2. Course Information • Course staff • Responsible: Dr. Zhonghai Lu, zhonghai@kth.se • Examiner: Prof. Axel Jantsch, axel@kth.se • Assistants: Huimin She, huimin@kth.se Abbas Eslami Kiasari, kiasari@kth.se • 12 Lectures, 4 Tutorials, 3 Labs • Home page: www.ict.kth.se/courses/IL2207/1201 • Course Material • Dally, Towles: Principles and Practices of Interconnection Networks • Distributed materials and slides • Advanced-level course, 7.5 credits, 40x5=200 hours SoC Architecture

3. Lecture Overview • L1: Introduction • L2: Buses and Arbitration (Dally: 22, 18) • L3: Shared Memory Multiprocessors • L4: Cache Coherency Protocols • L5: Memory Consistency • L6: Introduction to Network-on-Chip, Topologies (Dally: 1, 2, 3, 4, 5) • L7: Routing Algorithms and Mechanics (Dally: 8, 9, 10, 11) • L8: Flow Control (Dally: 12, 13) • L9: Deadlock and Livelock (Dally: 12, 13, 14) • L10: Router Architecture and Network Interface (Dally: 16, 17, 20) • L11: Network Performance Analysis and Quality of Service (Dally: 23, Dally 15) • L12: Course Summary SoC Architecture

4. Tutorial Overview • T1: Bus, arbitration and cache coherency • T2: Memory consistency and network topology • T3: Interconnection networks (routing, flow control, deadlock etc.) • T4: Router architecture, QoS and performance analysis • Tutorials will be given by Abbas. • For each tutorial questions, 2 Questions should be answered and handed in to Abbas before each tutorial session. 10% for the final grade. SoC Architecture

5. Lab Overview • Laboratory 1: Uniprocessor SoC Design on FPGA  • Assistant: Huimin • Laboratory 2: Multiprocessor SoC Design with Altera FPGA • Assistant: Huimin • Laboratory 3: Wormhole Networks • Assistant: Abbas • Each lab has 1 session • Students work in groups of max. 2 students • Good preparation is required. • Take good care of the FPGA boards. SoC Architecture

6. Course Requirements To pass the course the student has to fulfill the following requirements: • Pass the final exam. The grade for the exam will be the 90% grade of the course: ABCDEFxF • Final exam: March 13, 2012, 15-18:00, Ka438 • Register the exam in Daisy 2 weeks before the exam date in order to guarantee a seat ! • Complete all labs: Pass | Fail • Hand in tutorial results before each tutorial, 10% of grade • Attend lectures, tutorials and labs SoC Architecture

7. Labs • 3 labs in total • Lab 1 and 2: FPGA board. (Assistant: Huimin She huimin@kth.se ) • Lab 3: Network simulator. (Assistant: Abbas Eslami Kiasari kiasari@kth.se ) • Lab partners • Two persons in a group • If you also take IL2212 Embedded Software, please choose the same partner as you have for IL2212 • The FPGA boards must be returned after lab 1

8. Observations in System Design

9. Observations • Good news • Chip capacity increases following the Moore’s law • Functionality increases accordingly to exploit these transistors • Bad news • Difficult to design, Productivity decreases • Cost increases • Platform-based design can reduce cost • Architecture is a key! SoC Architecture

10. Intel 4004 (1971) 108 KHz 2,300 transistors If automobile speed had increased similarly over the same period, we could now drive from Stockholm to Shanghai in about 23 seconds. Advances in Integration Intel Pentium 4 (2000) 1.5 GHz 42 million transitors SoC Architecture

11. Intel chips with Moore’s law Seminar at National Institute of Informatics, Tokyo

12. 130 nm, 5.2 mm2 90 nm, 2.6 mm2 65 nm 1.4 mm2 Scaling ARM9 ARM 9 180 nm 11.8 mm2

13. Design Productivity Crisis Potential Design Complexity and Designer Productivity 10,000 100,000,000 Equivalent Added Complexity 1,000 10,000 Logic Tr./Chip 58%/yr compounded Complexity Growth Rate Tr./S.M. 1,000 100 100 10 Logic Transistor per Chip (M) 10 1 Productivity (K) Trans./Staff – Mo. 21%/yr compounded Productivity Growth Rate x x 1 0.1 x x x x x x 0.1 0.01 0.01 0.001 1985 1989 1987 1983 1991 1993 2009 1981 1995 1997 2007 1999 2001 2003 2005 Growing Design-Productivity Gap Designs do not only get more complex, but also much more expensive! SoC Architecture

14. The Role of the Market! Source: Smith 1997 Time-to-Market pressure! SoC Architecture

15. Verification Costs • The percentage of the verification costs of the total design costs is continuously increasing (at present 50-70% for large designs) SoC Architecture

16. RTL function 1 Processor RTL function 2 RTL function 3 Yesterday’s SOC Memory RTL I/O RTL RTL RTL Ctl Proc RTL RTL RTL RTL RTL Today’s SOC RTL Mem RTL RTL RTL RTL RTL DSP RTL I/O RTL RTL Mem Moore’s Law drives the development of System-in-Chip Architectures The growing number of transistors on an SOC drives the trend towards more RTL blocks on the chip Source: Leibson (DAC2004) SoC Architecture

17. From ASIC to SoC, MPSoC • We get more and more cores on a single chip SoC: both hardware and software (processor plus memory) ASIP: Application Specific Instruction Set Processors

18. Platforms reduce Costs SOC Flexibility = Per-Unit Cost Reduction (Model: 100K and 1M system volumes) Source: Leibson 2004 Low-endstill camera High-endstill camera Total per unit cost Video camcorder System designs per chip design One Chip Many System Designs $10M design cost, $15 manf. cost, 5% premium for programmability SoC Architecture

19. Platform Example: Nexperia SoC Architecture

20. Nexperia Instance: Viper SoC Architecture

21. Arm based MPSoC Platform SoC Architecture

22. OMAP from Texas Instruments • TI’s OMAP (Open Multimedia Application Platform) is a category of proprietary system on chips that has capabilities for portable and mobile multimediaapplications. • A number of mobile phones use OMAP SoCs. SoC Architecture

23. OMAP: Hierarchy of Platforms • OMAP uses platforms on different levels • This is a precondition for reuse Application Specific Ref Design Appl. Platform OMAP Products OMAP Infrastructure SoC Platform ASIC Library & Tools Reuse Silicon Technology SoC Architecture

24. SoC Platform • The SoC platform consists of • A library of hardware components • An architecture for their interconnection • The Application Platform • Processor and Peripherals • Low-Level Software (Drivers) • Development Environment • The System Platform • OS and Middleware • Includes the code that controls all aspects of the system from device driver to system interface • Compilers and tools SoC Architecture

25. OMAP 1510 • OMAP 1510 is based on • Enhanced ARM 925 core (RISC processor) • TI C55x core • DMA, SRAM, Busses, Peripherals SoC Architecture

26. Current OMAP platform for Wireless Handset & PDA • OMAP™ 3 architecture combines mobile entertainment with high performance productivity applications (Source: Texas Instruments) SoC Architecture

27. Evolving SoC Architectures

28. Memory FPGA Micro- controller Analog- Digital Digital- Analog Communication Structure Custom Hardware DSP System-on-Chip Architectures • A system-on-chip architecture integrates several heterogeneous components on a single chip • A key challenge is to design the communication between the different entities of a SoC in order to minimize the communication overhead SoC Architecture

29. Questions on Interconnects • To interconnect 2 IP hardware blocks, how would you like to let them communicate with each other? • What if 5 to10 IP modules? • What if 20 IP blocks? • What if 200 IP blocks? SoC Architecture

30. Memory Micro- processor DSP Custom Logic I/O System-on-Chip Architecture:A bus-based SoC System on a chip SoC Architecture

31. Technology Impact on Communication • Chip • Computation, storage by transistors • Communication by wires • How technology scaling affect communication delay? SoC Architecture

32. Scaling and Delays • Transistors are “free”; wires are “expensive”, slowing down performance. • Long wires should be avoided, and the whole chip cannot be treated as a monolithic piece and is preferably segmented into communicating regions. SoC Architecture

33. Number of Cores on Chip By ITRS (International Technology Roadmap for Semiconductors).

34. Communication architectures • Evolving from buses to networks • Buses are not scalable in bandwidth, power and performance • Network-on-Chip provides • Scalable architectures • Concurrent pipelined communication SoC Architecture

35. System-on-Chip Architecture: Network-on-Chip Switch • The resources are connected to the network via network interfaces • The topology of the network and the capability of the switches and communication channels determine the capacity of the network PE3 PE1 NI NI Resource Channel PE2 MEM NI NI Network Interface SoC Architecture

36. Intel Teraflop Chip - 2007 • 80 Cores • 100 Million transistors • 65nm process • 3.16 GHz • 0.95V • 62 W • 1.62 Terabit/s aggregate bandwidth • 91 Gb/s bisection bandwidth • 1.01 Teraflops

37. Tilera Gx Family • 4x4, 6x6, 8x8, 10x10 Chips • 3 instructions per cycle per core • 32 MB on chip cache • 750 GOPS (32 bit operations) • 200 Tbps on chip interconnect bandwidth • 500 Gbps memory bandwidth • ~ 1 GHz operating frequency • 10W – 55W power consumption • 5 mesh networks: 32 bit; Dimension order routing; 1-2 cycle traversal • Static Network (STN) • User Dynamic Network (UDN) • I/O Dynamic Network (IDN) • Tile Dynamic Network (TDN) • Memory Dynamic Network (MDN) SoC Architecture

38. Questions on Network Design • Network does • 1 to 1 communication: unicast • 1 to N communication: multicast • N to 1 communication: gather • 1. What problems needed to solve in order to realize unicast? 2. What performance metrics do you envision? 3. What factors influence the network performance? SoC Architecture

39. In the Course • Bus-based architectures • Buses and arbitration • Shared memory multiprocessors • Cache coherency • Memory consistency • Network-on-Chip (NoC) architectures • Topology • Routing • Flow control • Performance analysis SoC Architecture