Compiler-Based Register Name Adjustment for Low-Power Embedded Processors

1. Compiler-Based Register Name Adjustment for Low-Power Embedded Processors Peter Petrov; Alex Orailoglu;ICCAD’03

2. Agenda • Introduction • Mathematical Formulation • Heuristic Solutions For RNA • Register PermuTation (RPT) • Register PerturBation (RPB) • Experimental Results • Conclusions

3. Introduction • Objective: Low-Power • Key Point: Reduce bit transition activity on the register index streams. • Concept: Register Name Adjustment (RNA)

4. Example add r3, r2, r4 add r6, r2, r4 sub r6, r3, r5 sub r7, r6, r5 sub r3, r2, r6 sub r6, r2, r7 mul r4, r4, r5 mul r4, r4, r5 011 110 011 100 010 011 010 100 100 101 110 101 110 111 110 100 010 110 010 100 100 101 111 101 Total Bit Transitions: 7 + 4 + 5 = 16 3 + 4 + 3 = 10

5. Agenda • Introduction • Mathematical Formulation • Heuristic Solutions For RNA • Register PermuTation (RPT) • Register PerturBation (RPB) • Experimental Results • Conclusions

6. Cost Function • fc(rega, regb): the hamming distance between rega and regb. • l: the lth column in an instruction. • M(Pi, j): a bijective mapping function from the original reg Pi, j to a new reg index

7. Literals • Literals: unchangeable field in an instruction such as an opcode or immediate oprand. • L(i, j): to record the literal positions. if Li, j = 0 if Li, j = 1

8. Example v5 v1 0 v3 v2 v5 v4 v3 v2 v3 v4 v3 v3 v7 10 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ld r5, (r1) 0 add r3, r2, r5 add r4, r3, r2 mul r3, r4, r3 st r3, r7 (10) P = L = (v3, v4) – 3 (v4, v7) – 1 (v1, v2) – 1 (v2, v3) – 2 (v5, v2) – 1 (v5, v3) – 1 ( 0, v5) – 1 (v3, v3) – 1 (10, v3) – 1

9. Agenda • Introduction • Mathematical Formulation • Heuristic Solutions For RNA • Register PermuTation (RPT) • Register PerturBation (RPB) • Experimental Results • Conclusions

10. Select Vi and Vj that maximize f(eij) + f(eji) Pick names for Vi and Vj and compute the cost All unassigned indices tried? No Yes Name Vi and Vj with min cost No All registers named? Yes Finish Flow RPB: Max the distribution skew of register pair occurrences Time-Consuming Brute-Force

11. Literali … Literalj … Regi … Regj … Cost Function of RPT Cij = eij Vj Vi eji

12. Register PertuBation • Number of higher utilization frequency↓ Performance↑ • Number of self transition↑ Performance↑

13. Cost Function of RPB D: the number of self-transitions Maximize σto maximize the distribution skew of register pair occurrences Does larger σ imply larger skewness?

14. r1  r2, r3 r1 r2, r3 r4 r1, r2 r2 r1, r2 r2  r3, r4 r2 r3, r2 r1  r2, r3 r1 r2, r3 r4  r1, r2 r4 r2, r1 Register PertuBation • Commutativity Transformation • Dead Register Reassignment Question: would the data dependency increase? Note: these instructions must be commutable Note: r4 must be dead after the third instruction

15. r1 r2 r3 3 3 1 1 2 2 4 4 6 6 5 5 7 8 8 Dead Register Reassignment r1 r2 r3 Self-Transition 7

16. Agenda • Introduction • Mathematical Formulation • Heuristic Solutions For RNA • Register PermuTation (RPT) • Register PerturBation (RPB) • Experimental Results • Conclusions

17. Experimental Results Does larger σ imply larger skewness?

18. Agenda • Introduction • Mathematical Formulation • Heuristic Solutions For RNA • Register PermuTation (RPT) • Register PerturBation (RPB) • Experimental Results • Conclusions

19. Conclusions • Minimize the bit transitions , reduce the power consumption. • RPT improves up to 25%. • RPB improves up to 44%.