Testing elements in a fast communication channel 100gb s
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Testing elements in a fast communication channel 100GB/s. Midterm Presentation Spring 2010. Developers: Hanna Alam and Yousef Badran Project supervised by: Mr. Yossi Hipsh. Abstract. One of the major goals was to examine the current technologies and it’s boundaries . The road so far :

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Testing elements in a fast communication channel 100gb s

Testing elements in a fast communication channel 100GB/s

Midterm Presentation

Spring 2010

Developers: Hanna Alam and Yousef Badran

Project supervised by: Mr. Yossi Hipsh


Abstract

Abstract

  • One of the major goals was to examine the current technologies and it’s boundaries .

  • The road so far :

    • Getting to know today's technology and look up parts that are 100GB/s compatible

    • Studying the theoretical aspect of the Phase Lock Loop

    • Testing the PLL in an Evaluation Board

    • Measuring low frequency signals ranging 3~4GB/s

    • Summing up the results and recommending suitable technology to upgrade to 100GB/s


Testing elements in a fast communication channel 100gb s

  • Getting to know today's technology and look up parts that are 100GB/s compatible

  • We need to understand how the transmitter, receiver and medium work in 25GB/s transfer rate

  • What kind of components should we adapt for high frequency ?

  • Transistors, Diodes, Mixers, Counters, Flip-Flops, Amplifiers ...

  • What are their properties and how to catalogue them ?


Testing elements in a fast communication channel 100gb s

  • Studying the theoretical aspect of the Phase Lock Loop

  • What is a PLL ?

  • PLL is a control system that generates a signal that has a fixed relation to the phase of a "reference" signal, it responds to both the frequency and the phase changes of the input signals

  • How it’s related to our project ?


Testing elements in a fast communication channel 100gb s

  • Testing the PLL in an Evaluation Board

  • We’ll examine and work with ADF4350 PLL in particular

  • The goal is to use the PLL in a Eval-ADF4350EB1Z evaluation Board

  • Testing it in a free running mode and in locked mode

  • Different frequencies…

  • Relaxation period and stability for each frequency


Eva board block diagram

Eva-Board Block Diagram

  • Eval-ADF4350EB1Z

  • ADF4350

  • USB connector

  • Software

  • Output connectors


Testing elements in a fast communication channel 100gb s

  • Measuring low frequency signals

  • Measuring low frequency signals ranging 3~4 GHz

  • Generate signals using HP-8133A

  • Pulse generator

  • Infiniium DSO80204B Oscilloscope

  • to measure signals

  • Understanding the measuring methods to be able to chose the next generation measuring technology


Testing elements in a fast communication channel 100gb s

  • Summing up the results and conclusions

  • Gathering useful 100GB/s compatible devices on one catalogue

  • Suggesting ideas to how would be possible to work in 100GHz frequency with a stable signal

  • Suggesting tools and ways to measure a signal in a high frequency of 100GHz


Timeline

Timeline

We’ve created a grant timeline in order to keep track of our work

Estimated timeline:

Examining today’s technology 18/03 to 08/04

Looking up devices 08/04 to 20/04

Learning about PLL 22/04 to 07/05

ADF4350 Evaluation Board 13/05 to 08/06

Measuring Signals 06/06 to 21/06


Testing elements in a fast communication channel 100gb s

Questions?

Thank you…


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