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Chapter 5b: Single-cycle CPU Control. Registers. Read reg. num A. Read reg num A. Read reg data A. Read reg num B. Write reg num. Read reg data B. Write reg data. What do we need to control?. Mux - are we branching or not?. Registers- Should we write data?. 0. 4. Result. 1.

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Chapter 5b: Single-cycle CPU Control

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Chapter 5b single cycle cpu control

Chapter 5b:

Single-cycle CPU Control


What do we need to control

Registers

Read reg. num A

Read reg num A

Read reg data A

Read reg num B

Write reg num

Read reg data B

Write reg data

What do we need to control?

Mux - are webranching or not?

Registers-

Should we write data?

0

4

Result

1

Mux - Result fromALU or Memory?

Add

Result

Sh.Left2

Add

Read address

Data Memory

Read address

PC

Zero

Read data

1

Instruction [31-0]

Write address

Result

InstructionMemory

0

0

Write data

1

16

32

signextend

Mux - Wheredoes 2nd ALUoperand come from?

Memory-Read/Write/neither?

ALU -What is theOperation?

Almost all of the information we need is in the instruction!

5.3


Instructions opcode and function code

OpcodeRSRTRDShAmtFunction

OpcodeRSRTImmediate Data

OpcodeImmediate Data

Instructions – Opcode and Function Code

R-Type

I-Type

J-Type

Main instruction info is in the Opcode, which can be used to set up the datapath and the primary ALU (for I- and J-types)

For R-type instructions, the Function Code determines the function of the primary ALU (add, sub, mul, div, slt, and, or, etc.)

5.3


Decoding the instruction data

31-26

25-21

20-16

15-11

10-6

5-0

OpcodeRSRTRDShAmtFunction

31-26

25-21

20-16

15-0

OpcodeRSRTImmediate Data

Decoding the Instruction - Data

The instruction holds the key to all of the data signals

R-type

To ctrllogic

Readreg. A

Readreg. B

Writereg.

To ALUControl

Not Used

Memory,Branch

To ctrllogic

Readreg. A

Writereg./Readreg. B

Memory address or Branch Offset

One problem - Write register number must come from two different places.

5.3


Instruction decoding

Registers

Read reg. num A

Read reg num A

Read reg data A

Read reg num B

Write reg num

Read reg data B

0

Write reg data

1

We can decode the data simply by dividing up the instruction bus

Instruction Decoding

0

Opcode: [31-26]

4

Result

1

Add

Result

Sh.Left2

Add

Op:[31-26]

Ctrl

Rs:[25-21]

Read address

Rt:[20-16]

Data Memory

Read address

PC

Zero

Read data

1

Instruction [31-0]

Write address

Result

InstructionMemory

0

0

Write data

Rd:[15-11]

1

Read Reg A: Rs

Imm:[15-0]

16

32

signextend

Read Reg B: Rt

Write Reg: Either Rd or Rt

Immediate Data: [15-0]

5.3


Control signals

Registers

Read reg. num A

Read reg num A

Read reg data A

Read reg num B

Write reg num

Read reg data B

0

Write reg data

1

Control Signals

0

4

1:LW,R-type0:SW,Branch

1: Branch taken

0:Others

Result

1

Add

Result

Sh.Left2

PCSrc

Add

Op:[31-26]

1:SW0:others

1:LW0:others

Ctrl

MemWrite

RegWrite

MemToReg

ALUSrc

Rs:[25-21]

Read address

Rt:[20-16]

Data Memory

1: Memory0: R-type,Branch

Read address

PC

Zero

Read data

1

Instruction [31-0]

Write address

Result

InstructionMemory

0

0

Write data

Rd:[15-11]

1

RegDest

1:R-type

0:I-type

Imm:[15-0]

MemRead

16

32

signextend

?

1: LW

0: Others

5.3


The primary alu

Operation

A

Zero

Result

OverFlow

B

Cout

The Primary ALU

  • The Primary ALU is right in the middle of everything...

  • It must:

    • Add, Subtract, And, Or, etc. for R-types (from FC)

    • Subtract for a BEQ (from Opcode)

    • Add to determine address for a LW, SW (from Opcode)

Function OperationResult

And000R = A • B

Or010R = A Ú B

Add100R = A + B

Subtract101R = A - B

SLT111R = 1 if A < B

0 if A ³ B

5.3


Setting the alu controls

Setting the ALU controls

Main Control Logic generates ALUOp signal00: ALU adds01: ALU subtracts10: ALU looks at F.C.11: Unused

  • The instruction Opcode and Function give us the info we need

    • For R-type instructions, Opcode is zero, function code determines ALU controls

  • For I,J-type instructions, Opcode determines ALU controls

InstructionOpcodeALUOpFunct. CodeALU actionALU controladd00000010100000add100

sub000000 10100010subtract101

and000000 10100100and000

or000000 10100101or010

SLT000000 10101010SLT111

load word01001100xxxxxxadd100

store word01101100xxxxxxadd100

branch equal00010001xxxxxxsubtract101

5.3


Alu control signals

Registers

Read reg. num A

Read reg num A

Read reg data A

Read reg num B

Write reg num

Read reg data B

0

Write reg data

1

6

ALU Control Signals

0

4

Result

1

Add

Result

Sh.Left2

PCSrc

Add

Op:[31-26]

Ctrl

MemWrite

RegWrite

MemToReg

ALUSrc

Rs:[25-21]

Read address

Rt:[20-16]

Data Memory

Read address

PC

Zero

Read data

1

Instruction [31-0]

Write address

Result

InstructionMemory

0

0

Write data

Rd:[15-11]

1

RegDest

Imm:[15-0]

00: Add01: Sub10: R-type

ALUCtrl

MemRead

16

32

signextend

FC:[5-0]

ALUOp

ALU Control - A function of:

ALUOp

and the function code

5.3


Inside the control oval

Inside the control oval

00:Mem01:Branch10:R-type

1:Mem0:ALU

0:Reg1:Imm

  • This control logic can be decoded in several ways:

    • Random logic, PLA, PAL

  • Just build hardware that looks for the 4 opcodes

    • For each opcode, assert the appropriate signals

0:Rt1:Rd

1:Branch

RegALUMemRegMemMemInstructionOpcodeWriteSrcTo RegDestReadWritePCSrcALUOp

R-format000000100100 010

LW100011111010 000

SW10101101xx01 000

BEQ00010000xx00 101

Note: BEQ must also check the zero output of the ALU...

5.3


Control signals1

We must ANDBEQ and Zero

Registers

Read reg. num A

Read reg num A

Read reg data A

Read reg num B

Write reg num

Read reg data B

0

Write reg data

1

6

Control Signals

0

4

Result

1

Add

Result

Sh.Left2

Add

PCSrc

BEQ

Ctrl

MemToReg

MemRead

MemWrite

Op:[31-26]

ALUOp

ALUSrc

RegWrite

RegDest

Rs:[25-21]

Write

Read

Read address

Rt:[20-16]

Data Memory

Read address

PC

Zero

Read data

1

Instruction [31-0]

Write address

Result

InstructionMemory

0

0

Write data

Rd:[15-11]

1

Imm:[15-0]

ALUCtrl

16

32

signextend

FC:[5-0]

5.3


Jumping

32

1

28

26

0

4

Registers

Read reg. num A

Read reg num A

Read reg data A

Read reg num B

Write reg num

Read reg data B

0

Write reg data

1

6

Jumping

Sh.Left2

Concat.

0

4

Result

1

[31-28]

Add

Result

Sh.Left2

PCSrc

Add

Jump

J:[25-0]

BEQ

Ctrl

MemToReg

MemRead

MemWrite

Op:[31-26]

ALUOp

ALUSrc

RegWrite

RegDest

Rs:[25-21]

Write

Read

Read address

Rt:[20-16]

Data Memory

Read address

PC

Zero

Read data

1

Instruction [31-0]

Write address

Result

InstructionMemory

0

0

Write data

Rd:[15-11]

1

Imm:[15-0]

ALUCtrl

16

32

signextend

FC:[5-0]

5.3


Performance

Performance

What major functional units are used by different instructions?

R-type:Instr. FetchRegisterReadALURegisterWrite

6ns

LW:Instr. FetchRegisterReadALUMemory ReadRegisterWrite

8ns

SW:Instr. FetchRegisterReadALUMemory Write

7ns

Branch:Instr. FetchRegisterReadALU

5ns

Jump: Instr. Fetch

2ns

Assume the following times:

Since the longest time is 8ns (LW),the cycle time must be at least 8ns.

Memory Access: 2ns

ALU: 2ns

Registers: 1ns


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