Weak SRAM Cell Fault Model and a DFT Technique

1. Weak SRAM Cell Fault Modelanda DFT Technique

2. Outline • Background and motivation • SRAM issues: noise, SNM, weak cells • SRAM SNM sensitivity analysis • vs. process variation • vs. non-catastrophic defect resistance • vs. operating conditions • Programmable weak SRAM cell fault model • DFT for weak cell detection • Detection concept • Implementation • Conclusions

3. Noise Sources Static Dynamic • Process offsets and mismatches • Operating conditions variations • Cross-talk • Ripples in power rails • -particles Most of dynamic sources are quasi-static

4. What is SNM? SNM= max static noise, which can be tolerated by an SRAM cell without changing its logical state Seevinck et al, JSSC’87

5. What is a weak SRAM cell? Let’s consider a standard 6T SRAM cell:

6. What is a weak SRAM cell? Weak cell= a cell with inadequate SNM that can be easily flipped

7. Why Test Weak SRAM Cells? Because weak SRAM cells: • Prone to stabilityfaults • Manifestreliability problems • Can signify defects, which… • Escape regular march tests

8. What Does SNM Depend On? • Process variation (mismatch / offset): • VTH spread • LEFF, WEFFspread • Resistance of non-catastrophic defects: • RBREAK • RBRIDGE • Operation conditions: • VBL • VDD • VWL • T0C

9. Static Noise Marginas a Function of Process Variation all results for 0.13um technology, read-accessed cell, i.e. VWL=VBL=VDD

10. SNM vs. VTH (Single Transistor) • Typical process corner • SNM=100% @ zero VTH deviation • Driver  strongest impact, load  weakest impact

11. SNM vs. VTH (Single Transistor) • Typical + slow process corners • For slow: SNM>100% @ zero VTH deviation

12. SNM vs. VTH (Single Transistor) • Typical + slow +fast process corners • For fast: SNM<100% @ zero VTH deviation

13. SNM vs. VTH (Multiple Transistors) • Typical process corner • One VTH changes, while some other are biased • Strong SNM decline for some VTH combinations (at max asymmetry)

14. SNM vs. Leff and Weff (Single Transistor) • SNM=100% for typical geometry • Geometry variations – weak impact on SNM (max 7%)

15. Static Noise Marginas a Function of Non-Catastrophic Defect Resistance

16. SNM vs. Break Resistance •  Rbreak  SNM • SNM vs. gate breaks  weak dependence • SNM vs. driver breaks  strong dependence

17. SNM vs. Bridge Resistance •  Rbridge  SNM • SNM vs. Rbridge uniform dependence

18. Static Noise Marginas a Function of Operation Conditions

19. SNM vs. Bit Line Voltage • Typical process • If VBL>0.8V SNM=100% • If VBL<0.35V SNM=0% - hard failure ( normal write) • If 0.35V<VBL>0.8V SNM linearly 

20. SNM vs. Bit Line Voltage • Typical + slow process corners • VBL>0.8V SNM>100% • VBL<0.35V SNM=0% - hard failure (or normal write) • 0.35V<VBL>0.8V SNM linearly 

21. SNM vs. Bit Line Voltage • Typical + slow +fast process corners • VBL>0.8V SNM<100% • VBL<0.35V SNM=0% - hard failure (or normal write) • 0.35V<VBL>0.8V SNM linearly 

22. SNM vs. Global VDD • Typical + slow +fast process corners (extreme cases) • SNM linearly 

23. SNM vs. Local VDD • Local  resistive break in local VDD • Typical + slow +fast process corners (extreme cases) • @VDD_LOCAL<0.8V SNM=0 • @VDD_LOCAL>0.8V SNM linearly 

24. SNM vs. Word Line Voltage • Typical process • Read-accessed SRAM cell (SNM deviation @VWL=VDD0%) • @VWL <VTH_ACCESS SNM=max • @VWL >VTH_ACCESS SNM linearly 

25. SNM vs. Word Line Voltage • Typical + slow process corners

26. SNM vs. Word Line Voltage • Typical + slow +fast process corners

27. SNM vs. Temperature • Weak dependence • 10% max (fast ) • 2.5% min (slow)

28. Proposed Weak Cell Fault Model and a Programmable DFT Technique

29. Weak cell fault model • SNM vs. node-node R • @Rnode-node[50k,500k] – linear dependence

30. Weak cell fault model • Resistor between nodes A and B • Which is equivalent to • Negative feedback for inverters of an SRAM cell

31. Programmable detection concept

32. Programmable detection concept • @ VTEST: • weak cell flips • good cell does not flip

33. Proposed DFT concept • Changing of ratio R brings nodes to different potentials • Weak cell will flip and will be detected • Good cell will retain data

34. Proposed DFT Algorithm • Write background ratio of zeroes and ones • Normal precharge • Enable n word lines • Right after that short bit lines • Release word lines • Release bit lines

35. Proposed DFT Implementation • Write background ratio of zeroes and ones • Normal precharge • Enable n word lines • Right after that short bit lines • Release word lines • Release bit lines

36. Proposed DFT Simulation Results • Rweak=200k (~65% SNM) • Five “0”, three ”1” • Weak cell is detected!

37. Proposed DFT Simulation Results • Rweak=200k (~65% SNM) • Three “0”, five ”1” • Weak cell is not detected

38. Proposed DFT detection capability • Rweak=100k-500k • Five “0”, three ”1” • Weak cell flips for Rweak<200k

39. Conclusions • Weak SRAM cells can escape march tests  need DFT • Cell stability is sensitive to process and operation disturbances • Weak cell fault model is essential in developing test techniques • Proposed DFT efficiently detects weak SRAM cells, i.e. cells with inadequate SNM