IXP 2400. 4 Types of registers: General purpose. Synchronous Random Access Memory transfer (SRAM). Dynamic Random Access Memory transfer (DRAM). Next Neighbor (NN). Registers. 256 for each Microengine. 32 Bits. Divided in 2 banks of registers (A and B).
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When data is read from other functional units, it is placed in SRAM transfer registers.
//Setup a value to write into memory
//Set bit 31 in the Write Xfer.
Alu_shf[$my_xfer_reg, --, B, 1, <<31]
Alu_shf[$my_xfer_reg, $my_xfer_reg, OR, ctx]
The first ALU shift modifies the Write register called my_xfer_reg.
The second instruction logically OR´s the context number to the read transfer register and places the results into de transfer register.
The T_INDEX register is first loaded with the transfer register number to access (0-127) then the pseudo-register *$index is used to access the SRAM transfer register indicated by the T_INDEX register.
Configured in mode 2, two CSRs in each microengine allow the code to treat the next-neighbor register as a 128-entry queue.
Each memory has logical width that determines the minimum number of bytes that are accessed during any memory operation.