1 / 11

System and Circuit Level Power Modeling of Energy- Efficient 3D -Stacked Wide I/ O DRAMs

System and Circuit Level Power Modeling of Energy- Efficient 3D -Stacked Wide I/ O DRAMs. Karthik Chandrasekar TU Delft. Christian Weis $ , Benny Akesson*, Norbert Wehn $ & Kees Goossens #. *. $. #. Overview. Motivation for 3D-stacking of DRAMs Problem Statement - Power Modeling

aren
Download Presentation

System and Circuit Level Power Modeling of Energy- Efficient 3D -Stacked Wide I/ O DRAMs

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs Karthik Chandrasekar TU Delft Christian Weis$, Benny Akesson*, Norbert Wehn$ & Kees Goossens# * $ #

  2. Overview • Motivation for 3D-stacking of DRAMs • Problem Statement - Power Modeling • Circuit-level DRAM architecture & power model • System-level DRAM power model (DRAMPower) • Comparison: Results and Analysis • Summary Karthik Chandrasekar / TU Delft

  3. Motivation: Why 3D-Stacked DRAMs? [I/O power per bit: 0.7mW in TSV vs 2.3mW in PoP vs 4.6mW in Off-Chip – Samsung] The Performance Vs. Power Factor   We want 3D-Stacking! Images & Data Courtesy: HMC, JEDEC 42.6, FineTech, Nvidia, Samsung Karthik Chandrasekar / TU Delft

  4. What’s missing? [Problem Statement] An accurate 3D-DRAM Power Model to design DRAM-stacked SoCs Karthik Chandrasekar / TU Delft

  5. Approaches to power modeling • Circuit-level Power Model • Modeling the DRAM architecture at the circuit-level in SPICE • Pros: Accurate and detailed • Cons: Slow, requires circuit-level understanding of DRAM architecture & technology specifications for DRAMs are publicly unavailable • System-level Power Model (like Micron’s) • Based on vendor provided datasheet measures and JEDEC specifications • Pros: Fast, easy to integrate & employs simple models for memory operations • Cons: Accuracy is unclear. Not directly applicable for 3D-DRAMs and is not verified against circuit-level models or hardware measurements. Need: Fast, Simple & Accurate Model Karthik Chandrasekar / TU Delft

  6. What’s the solution? Develop A System-Level 3D-DRAM Power Model i.e. as accurate as A Circuit-Level 3D-DRAM Power Model Karthik Chandrasekar / TU Delft

  7. Circuit-Level DRAM Modeling Baseline DRAM Model • (Weis) DATE‘11 and DAC‘13 • NGSPICE - PTM/BSIM • 1T1C Cell to Banks 2D to 3D (New) • Based on DATE ‘11 & JEDEC Wide IO – x512 • 4 Banks/Channel • 4 Channels • TSV Routing • Data, Cmd & Addr • Control, Clock & Power • No ODT (On Die Termination) • Low Freq. & IO Capacitance • No DLL (Delay Locked Loop) • TSV model from IMEC/GaTech Karthik Chandrasekar / TU Delft

  8. System-Level Power Model (DRAMPower) Comparison to Micron model • Problem with Micron’s model: • Not directly applicable for 3D-DRAMs (Multiple voltage domains and IO) • Accuracy is unclear (State transitions not addressed & Approx. workload used) • Not verified against circuit-level models or hardware power measurements. • Adapting to 3D-DRAMs: • Considers multiple voltage domains: (a) Core (b) Derived (Wordline) • Includes IO power consumption (Incl. I/O Pads, Buffers, Bumps, Drivers & Pins) • RD operation Energy (Generic equation): • Modeling for Accuracy: • Models memory state transitions – from active to power-down • Models self-refresh accurately (functional correctness & timing difference) • Most importantly: Is almost as accurate as the circuit-level model Karthik Chandrasekar / TU Delft

  9. Self-Refresh Operation - Accuracy • Actual • Internal Refresh • No DLL We furnish new equations in the system-level power model to address such accuracy issues Karthik Chandrasekar / TU Delft

  10. Comparison: Results & Analysis • Experiment I: • Different Operations • Different Granularity • Results: • Less than 2% difference • Adapted Micron SR (200): 72% diff. • Experiment II: • H.263 Encoder & EPIC Encoder • JPEG Encoder & MPEG2 Decoder • Different Loads and Power Modes • Results: • Less than 2% difference • Adapted Micron: 12% diff. (SR 500MHz) • The 2% difference is due to the use of JEDEC-specified averaged IDD currents. Shows the accuracy of the system-level power model Karthik Chandrasekar / TU Delft

  11. Summary Key Highlights: • Presented an accurate datasheet-based system-level power model for Wide I/O 3D-stacked DRAMs. • Verified the system-level model for accuracy against as a detailed SPICE-based circuit-level 3D-DRAM architecture and power model. • Observed < 2% difference in power and energy estimates for different memory operations and for any variations in memory load. Other Important Contributions: • Provided estimates for IDD current measures for different JEDEC 3D-DRAM configurations, in place of the as yet unavailable datasheets (in the paper). • The system-level power model (DRAMPower) has been released online as an open-source 3D-DRAM power estimation tool. Download link: www.drampower.info Karthik Chandrasekar / TU Delft

More Related