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Fig 8-4 p-341. S 5 =IF flag (interrupt Enable). S 6 =0 always. - PowerPoint PPT Presentation


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Fig 8-4 p-341. S 5 =IF flag (interrupt Enable). S 6 =0 always. SSO=during read cycle, it is identifies whether a code or data access is in progress. Types of I/O for 8088/8086. Input/output system allows peripherals to: Provide data or Receive results after processing the data.

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Fig 8-4 p-341.

S5=IF flag (interrupt Enable).

S6=0 always.



Types of i o for 8088 8086
Types of I/O for 8088/8086 data access is in progress.

  • Input/output system allows peripherals to:

    • Provide data or

    • Receive results after processing the data.

  • Implemented using I/O ports.

  • Employs two different types of I/O:

    • Isolated I/O.

    • Memory mapped I/O.

  • Method differs in how I/O ports are mapped into MPU’s address spaces.

  • Some microcomputer employs both method.


Isolated i o
Isolated I/O data access is in progress.

  • I/O devices treated separately from memory.

    • Hardware and software architecture of 8088/8086 support separate memory I/O address space.

  • Can be accessed as either byte-wide or word-wide.

  • Can be treated as either independent byte-wide I/O ports or word-wide I/O ports.

  • Page 0:

    • Certain I/O instructions can only perform operations to ports in this part of the address range.

    • Other I/O instructions can input/output data for ports anywhere in the address space.


Isolated i o1
Isolated I/O data access is in progress.

Page 0

Port 1 (16 bit port)

Port 0 (16 bit port)


Isolated i o2
Isolated I/O data access is in progress.

  • Advantages:

    • 1 MByte memory address space is available for use with memory.

    • Special instructions have been provided in the instruction set of 8088/8086 to perform isolated I/O input and output operations.

      • These instructions have been tailored to maximize I/O performance.

  • Disadvantages:

    • All input and output data transfers must take place between AL or AX register and the I/O port.


Memory mapped i o
Memory-mapped I/O data access is in progress.

  • I/O devices is placed in memory address space of the microcomputer.

    • The memory address space is assigned to I/O devices.

    • MPU looks at the I/O port as though it is a storage location in memory.

    • Make use of instructions that affect data in memory rather than special input/output instructions.


Memory mapped i o1
Memory-mapped I/O data access is in progress.

I/O addresses

Port 1

(16 bit port)

Port 0

(16 bit port)


Memory mapped i o2
Memory-mapped I/O data access is in progress.

  • Advantages:

    • Many more instructions and addressing modes are available to perform I/O operations.

    • I/O transfers can now take place between I/O port and internal registers other than just AL/AX.

  • Disadvantages:

    • Memory instructions tend to execute slower than those specifically designed for isolated I/O.

    • Part of the memory address space is lost.


Isolated input output interface
Isolated Input/Output Interface data access is in progress.

  • The interface permits 8088/8086 microcomputers to communicate with the outside world.

  • The interface between MPU and I/O is similar to MPU and memory.

  • Input output data transfers also take place over the multiplexed address/data bus.

  • Through this I/O interface, the MPU can input or output data in bit, byte or word (8086) formats.


Isolated input output interface minimum mode interface
Isolated Input Output Interface :: Minimum-mode Interface data access is in progress.

Minimum-mode 8088 system I/O interface


Isolated input output interface minimum mode interface1
Isolated Input Output Interface :: Minimum-mode Interface data access is in progress.

Minimum-mode 8086 system I/O interface


Isolated input output interface minimum mode interface2
Isolated Input Output Interface :: Minimum-mode Interface data access is in progress.

  • Example of I/O device:

    • Keyboard (input).

    • Printer (output).

    • Asynchronous serial communications port (input/output).

  • Circuits in the interface section must perform functions such as:

    • Select I/O port.

    • Latch output data.

    • Sample input data.

    • Synchronize data transfers.


Isolated input output interface minimum mode interface 8088
Isolated Input Output Interface :: Minimum-mode Interface (8088)

  • Data/Address Lines:

    • Multiplexed address/data bus.

    • Only 16 least significant lines used.

      • AD0-AD7 and A8-A15.

  • Control Signals:

    • Similar to memory interface.

  • Difference between 8088 and 8086.

    • Complete data bus used for data transfer.

      • AD0-AD15.

    • M/IO complement of IO/M.

    • SSO replaced with BHE.


Isolated input output interface maximum mode interface
Isolated Input Output Interface :: Maximum-mode Interface (8088)

Maximum-mode 8088 system I/O interface

Maximum-mode 8086 system I/O interface


Isolated input output interface maximum mode interface 8088 86
Isolated Input Output Interface :: Maximum-mode Interface (8088/86)

  • 8288 bus controller produces control signals for the I/O subsystems.

  • Decoded S2S1S0 will determine which type of bus cycle is in progress.

  • If code corresponds to:

    • I/O read bus cycle , 8288 generates IORC.

    • I/O write bus cycle, then IOWC and AIOWC generated.

  • 8288 also produces ALE, DT/R and DEN control signals.

  • Data and addresses are transferred over AD0-AD7 and A8-A15.

  • 8086 differs from 8088 as follows:

    • 16 bit data bus is the path for data transfers.

    • Signal BHE is included.


Input output data transfers
Input Output Data Transfers (8088/86)

  • Data transfers:

    • Byte-wide or word-wide.

  • I/O address usedto select the input/output port to be accessed.

    • I/O address specified as part of the instruction that performs the I/O operation.

  • The addresses:

    • 16 bits in length.

    • Output over AD0 (LSb) – AD7 and A8-A15 (MSb).

  • The most significant address lines A16-A19 = 0 during address period (T1) of all bus cycles.

  • IO/M determines I/O operations. Held at 1 during the complete input/output bus cycles.


Input output data transfers1
Input Output Data Transfers (8088/86)

  • Data transfer (8088).

    • Performed over data bus.

    • Byte-wide transfers = 1 cycle (D0-D7).

    • Word-wide transfers require two bus cycles.

      • Two consecutive byte-wide data transfers.

  • Data transfer (8086):

    • The addresses are output on address/data bus lines AD0-AD15.

    • A0 and BHE determine whether access at odd-addressed byte-wide port, even-addressed byte-wide port or word-wide port.

      • i.e. A0BHE = 10  odd-addressed byte wide I/O port is accessed.


Input output data transfers2
Input Output Data Transfers (8088/86)

  • Even and odd addressed byte transfer require 1 bus cycle.

    • Even-addressed byte transfer  D0-D7.

    • Odd-addressed byte transfer  D8-D15.

  • Word data transfer can either require one or two bus cycles .

    • Word data transfer performed over D0-D15.

    • One cycle word transfer  I/O port is aligned at even address boundaries.

    • Two cycles word transfer  Misaligned word.


Input output instructions
Input Output Instructions (8088/86)

  • Isolated I/O mode uses special input and output instructions together with I/O port addressing modes.

  • Can either be direct or variable I/O instructions.

    • Can be used to transfer byte/word.

    • All data transfer take place over I/O device and accumulator register (AL/AX).

      • Known as accumulator I/O.

    • Byte/word wide transfer determined by AL/AX.


Input output instructions1
Input Output Instructions (8088/86)

Input/output instructions


Input output instructions direct i o instructions
Input Output Instructions :: Direct I/O Instructions (8088/86)

  • Address of the I/O port:

    • Specified as part of the instruction.

  • 8 bits provided for direct address, thus:

    • Address range is limited to 0016-FF16.

    • This range is referred as page 0 in I/O address space.

  • i.e. IN AL, 0FEH

    • (AL)  (FE16)

    • Content of address FE to be input to the AL register.

    • Only one bus cycle.


Input output instructions direct i o instructions1
Input Output Instructions :: Direct I/O Instructions (8088/86)

  • Example 2:

    • Write a sequence of instructions that will output the data 3416 to a byte-wide output port at address 8916 of the I/O address space.


Input output instructions2
Input Output Instructions (8088/86)

  • Difference between direct and variable:

    • The way in which the address of the I/O port is specified.

    • Direct  8 bit address is specified as part of the instruction.

    • Variable  use 16 bit address in DX register.

      • (DX) is not an offset but actual address.

  • Variable I/O instructions can access ports located anywhere in the 64 K byte I/O address space.

  • Data/address must be loaded into or removed from AL/AX/DX before another input or output operation can be performed.


Input output instructions3
Input Output Instructions (8088/86)

  • Example 2:

    • Write a program that will output DA16 to an output port located at address EA2016 of the I/O address space.

    • Data are to be read in from two byte-wide input ports at address AA16 and BA16 and then output as a word-wide output port at address B00016. Write a program to perform this input/output operation.


Input output bus cycles
Input Output Bus Cycles (8088/86)

  • Signals (minimum-mode) similar to those involved in memory interface.

  • Function, logic levels and timing of all signals other than IO/M are identical to section 8.11.

  • IO/M changes at logic level, not the timing.


Input bus cycles 8088
Input Bus Cycles :: 8088 (8088/86)

  • T1:

    • IO/M =1 and maintained throughout the cycle.

      • Indicate IO operation.

    • ALE output together with address.

    • DEN =0.

      • Signals interface circuitry when to put data onto the bus.

      • 8088 reads data off the bus during period T3.

Input bus cycle of the 8088


Output bus cycles 8088
Output Bus Cycles :: 8088 (8088/86)

  • 8088 puts data on the bus late in T2 and maintains it during the rest of the bus cycle.

  • This time WR = 0.

    • Signals I/O system that valid data are on the bus.

Output bus cycle of the 8088


Input bus cycles 8086
Input Bus Cycles :: 8086 (8088/86)

  • Differences:

    • BHE output along with address in state T1.

      • Used with A0 to select even/odd address byte/word wide port.

    • Data transfer over 16 bit address/data bus at T3.

    • M/IO replaces IO/M.

    • SSO = none.

      Refer figure 8-52 & 8-53


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