Diagnosis and Correction of Logic Design Errors in Circuits

1. Diagnosis and Correction of Logic Design Errors in Circuits Student: Yu-Lin Hsiao Advisor: Chun-Yao Wang 2006.5.24 Department of Computer Science National Tsing Hua University, Taiwan

2. Outline • Introduction • Previous work • Problem description • Diagnosis method • Future work

3. Introduction • With the increase in circuit complexity, a few logic design errors can easily occur. • Error diagnosis and correction not only can fix implementation errors but also can be useful in engineering change (EC) problem.

4. Introduction (Cont’d) • The solution space grows exponentially with the number of circuit lines and the number of error models: (# ckt lines)(# errors) • With the increase of errors occur in a circuit, this problem is more difficult to get a satisfied solution.

5. Previous work • Simulation-based approach ．By simulating input vectors, try to guess the error locations, and the potential error region can be pruned gradually. ．Three heuristic methods: Cone Intersection, Sensitization-based Filter, Back Propagation. • Symbolic approach ．It rely on OBDD to formulate the necessary and sufficient condition of a single fix signal.

6. Previous work (Cont’d) • Simulation-based approaches are primarily filters. and can produce satisfactory diagnosis results. • But they don’t provide enough insight about how to fix the errors. • Symbolic approaches not only can pin-point the exact error locations, but also suggest a way to fix the design. • But they may cause memory explosion for large circuits. • Symbolic approaches are more accurate than the simulation-based approaches and also extendible to multiple errors.

7. Problem Description • Given two netlists C_org and C_opt C_org is the original circuit C_opt is the timing/area optimal circuit • If at least one function among both circuits is not equivalent, the C_opt is consider as having design errors.

8. Problem Description (Cont’d) • Assume there are a few simple design errors in the C_opt, and the error types are missing inverter or extra inverter. • C_opt: the internal nodes and POs nodes are visible. C_org: only POs nodes are visible.

9. Diagnosis method (1/9) • Backtrace rules OR gate: N1 N0 N1 N1 N0 N1 N0 N1 N0 Y0 Y0 Y0 Y0 N1 N1 N0

10. Diagnosis method (2/9) • Backtrace rules AND gate: N0 N1 N0 N0 N1 N0 N1 N0 N1 Y1 Y1 Y1 Y1 N0 N0 N1

11. Diagnosis method (3/9) • Backtrace rules Inverter gate: N0 N1 N1 N0

12. Diagnosis method (4/9) • Based on backtrace rules, trace back all error bits. 1 2 2 a 2 1 2 1 8 654 21 2 b 1 1 2 1 2 11110100 1 2 1 2 2 1 c 1 2 1 1 01001111 1 2 1 2 {1,2,4,5,6,8}

13. Diagnosis method (5/9) • Record the sensitized error bits of the circuit wires. • Choose the wires that have most number of sensitized error bits as candidate error sources. • Examine all candidate error sources start with one which is nearest to PI .

14. Diagnosis method (6/9) • If a line is the error source, this line is sensitized most times. (single error) a 8 654 b 11110111 c 01001111 {4,5,6,8}

15. Diagnosis method (7/9) • Trace back the circuit in a parallel way. …………. {42} {421} 01010101 d a 01000100 e f {65421} m 8 654 21 b 00110011 11001100 01110100 g {654} o 11110100 n 00110011 00110000 c y i 11110000 h {65421} {65421} 00001111 j k 01001111 p 10101010 10100000 11110000 l {86421} …………... {86421}

16. Diagnosis method (8/9) • Use DFS to trace the circuit. y(124568) o(12456) p(12468) m(124) n(12456) j(168) l(12468) ………… k(12456) The maximum sets are candidate error source h(12456) h(124568) c(12456) c(124568)

17. Diagnosis method (9/9) • Issues: 1.How to examine the candidate error sources efficiently. 2.How to adjust our diagnosis method if there are more than one error in a circuit. 3.If there is no satisfied solution, how to make diagnosis method coverage.

18. Future work • Make diagnosis method more complete for multiple errors. • Try simple gate replacement error type. Develop its backtrace rules. • Survey Andreas Veneris’s and S. Abadir’s papers.