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Examples of Bus Standards. PCI & AGP. Overview. PCI ( Peripheral Component Interconnect) Technical description Protocol Data transfers Arbitration schemes AGP (Accelerated Graphic Port) Is AGP an attempt to replace PCI? . PCI – technical description. Pin Description

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Presentation Transcript
  • PCI ( Peripheral Component Interconnect)
    • Technical description
    • Protocol
    • Data transfers
    • Arbitration schemes
  • AGP (Accelerated Graphic Port)
  • Is AGP an attempt to replace PCI?
Pin Description
  • System Pins: Includes the clock and reset pins
  • Address and Data pins: 32 lines that are time-multiplexed for address and data. Other pins used to interpret and validate the signal lines that carry the info.
  • Interface Control Pins: Control the timing of transactions and provide coordination among masters (initiators) and slaves (targets)
  • Error Reporting Pins: Report parity and other errors (parity is a special kind of number used for error checking)
  • Arbitration Pins: Not Shared lines. Each PCI device that can act as a master has its own pair of arbitration lines that connect directly to the PCI bus arbiter
  • Interrupt Pins: Provided for PCI devices connected to bus that must generate requests for service. NOT shared lines. Each device has its own interrupt line or lines to an interrupt controller.
  • Cache Support Pins:Support memory on the PCI bus that can be cached in the processor or another device.
  • 64-bit Bus Extension Pins :32 more lines that are time-multiplexed for address and data info.
PCI Signal Description
  • AD(x) :Address/Data Lines.
  • CLK: Clock. 33 MHz maximum.
  • C/BE(x): Command, Byte Enable.
  • FRAME : Used to indicate whether the cycle is an address phase or a data phase.
  • DEVSEL: Device Select.
  • IDSEL: Initialization Device Select
  • INT(x): Interrupt
  • IRDY: Initiator Ready
  • LOCK: Used to manage resource locks on the PCI bus.
  • REQ: Request. Requests a PCI transfer.
  • GNT: Grant. indicates that permission to use PCI is granted.
pci protocols
PCI –protocols
  • The PCI bus uses a synchronous bus protocol with all data transfers being performed relative to a system clock.
  • It also uses non pipelined bus protocol. The address and data have a direct one to one correspondence.
pci data transfer
PCI – data transfer

Read and Write operations in the PCI bus

pci arbitration
PCI - arbitration
  • The PCI bus uses centralized arbitration with a parallel arbiter.
    • Round robin and prioritized arbitration are among the arbitration algorithms supported by the bus.
AGP was designed with two purposes:
    • To relieve the PCI bus of work with graphics data.
    • To have better bandwidth within the video system.
agp technical description
AGP – technical description
  • AGP is an extension of the PCI bus.
agp protocols
AGP - protocols

Aside from using the synchronous bus protocol, it follows the out of order bus protocol. AGP is a pipelined bus with the additional feature that the order of returning the data can be different than the order in which the addresses were received.

agp data transfers
AGP – Data transfers

AGP provides two modes for the graphics controller to directly access texture maps in system memory:

Pipelining –AGP overlaps the memoryor bus access times for a request (“n”) with the issuing of following requests

Sideband addressing – AGP uses 8 extra “sideband” address lines which allow the graphics controller to issue new addresses and requests simultaneously while data continues to move from previous requests on the main 32 data/address buses.
agp arbitration
AGP - arbitration
  • Similar to PCI – centralized, prioritized arbitration
Since AGP is a dedicated graphics connection used only by the graphics accelerator, the overall system performance is improved in two ways:
    • Graphics operations are faster
    • Other peripheral devices are also faster
is agp an attempt to replace pci
Is AGP an attempt to replace PCI?

AGP neither replaces nor diminishes the necessity of PCI in the system. It is physically, logically, and electrically independent of the PCI bus and forms an additional connection point in the system. It is intended for the exclusive use of graphic controllers; all other I/O devices will continue to reside on the PCI bus.