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Characterization of a CMOS cell library for low-voltage operation

Characterization of a CMOS cell library for low-voltage operation. Department of Electrical and Computer Engineering Jia Yao. Low-power and Low-voltage. Pavg = Pdyn + Pstatic Pdyn = Ptran + Pshort-circuit Ptran = α * C * Vdd 2 * f

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Characterization of a CMOS cell library for low-voltage operation

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  1. Characterization of a CMOS cell library for low-voltage operation Department of Electrical and Computer Engineering Jia Yao

  2. Low-power and Low-voltage • Pavg = Pdyn + Pstatic • Pdyn = Ptran + Pshort-circuit • Ptran = α * C * Vdd 2 * f • Pshort-circuit = Isc * Vdd CMOS: dynamic power Reduction of the power supply voltage is the most efficient way to reduce the power consumption.

  3. Concentration • Study TSMC 0.18um standard cell library • Design basic CMOS cells in Hspice and run simulation • Apply supply voltage from high to low to observe the influence of lowering Vdd • Collect data and arrive to conclusion

  4. Basic Parameters • The environment temperature : 25 ℃ • Input pulse T=24ns, and the width of input pulse is 12ns, so the frequency is 41.6MHz. • Input slew : 0.03ns • Channel length L=0.2um • Width Wn=2um, Wp=2.4um • Nmos:VTH0 = 0.3725327 Pmos: VTH0 = -0.3948389

  5. Vdd Vdd/2 Vdd/2 tphl tplh Vdd Vdd/2 Vdd/2 Calculation • Gate Delay= (tphl+ tplh)/2 • For two or more inputs gate, calculate delay separately. 1. Gate Delay in Vdd Vdd/2 Vdd/2 A Y tphl tplh B out Vdd • Without and with outloading Vdd/2 Vdd/2 A Y Y’ B

  6. Calculation 2. Power Calculation ※ Average power and Peak power ※ For two or more inputs, calculate power separately, keep only one signal changing at one time. ※ Without and with outloading

  7. Inverter

  8. Power-Delay Product

  9. Comparison : with and without outloading Delay Avg Power Peak Power Power-Delay Product

  10. Nand2

  11. Comparison : with and without outloading Delay Avg Power Peak Power Power-Delay Product

  12. NOR2

  13. Comparison : with and without outloading Delay Avg Power Peak Power Power-Delay Product

  14. Review • Around 1 V • With and without outloading • Separate calculation

  15. Reference • Class notes and slides from ELEC6270 by Dr. Agrawal 2. TSMC 0.18 um standard cell library data book 3. Hspice user guide • Boarh,M.; Owens, R.M.and Irwin, M.J, “Transistor sizing • For low power CMOS circuits’’ IEEE Trans. On Computer- • Aided Design of Integrated Circuits and System, vol.15, • pp.665-671, 1996

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