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CSE 502 Graduate Computer Architecture Lec 8-10 – Instruction Level Parallelism

CSE 502 Graduate Computer Architecture Lec 8-10 – Instruction Level Parallelism. Larry Wittie Computer Science, StonyBrook University http://www.cs.sunysb.edu/~cse502 and ~lw Slides adapted from David Patterson, UC-Berkeley cs252-s06. Outline. ILP – Instruction Level Parallelism

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CSE 502 Graduate Computer Architecture Lec 8-10 – Instruction Level Parallelism

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  1. CSE 502 Graduate Computer Architecture Lec 8-10 – Instruction Level Parallelism Larry Wittie Computer Science, StonyBrook University http://www.cs.sunysb.edu/~cse502 and ~lw Slides adapted from David Patterson, UC-Berkeley cs252-s06

  2. Outline • ILP – Instruction Level Parallelism • Compiler techniques to increase ILP • Loop Unrolling • Static Branch Prediction • Dynamic Branch Prediction • Overcoming Data Hazards with Dynamic Scheduling • (Start) Tomasulo Algorithm • Conclusion • Reading Assignment: Chapter 2 today, (Quiz back next class), Chapter 3 next. (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  3. Recall from Pipelining Review • Pipeline CPI = Ideal pipeline CPI + Structural Stalls + Data Hazard Stalls + Control Stalls • Ideal pipeline CPI: measure of the maximum performance attainable by the implementation • Structural hazards: HW cannot support this combination of instructions • Data hazards: Instruction depends on result of prior instruction still in the pipeline • Control hazards: Caused by delay between fetching of instructions and decisions about changes in control flow (branches and jumps {MIPS: j jump, jal call, jr return}) (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  4. Instruction Level Parallelism • Instruction-Level Parallelism (ILP): overlap the execution of instructions to run programs faster (“improve performance”) • Two approaches to exploit ILP: 1) Rely on hardware to help discover and exploit the parallelism dynamically (e.g., Pentium 4, AMD Opteron, IBM Power), and 2) Rely on software technology to find parallelism, statically at compile-time (e.g., Itanium 2) • Next 3 lectures on ILP (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  5. Instruction-Level Parallelism (ILP) • Basic Block (BB) ILP is quite small • BB: a straight-line code sequence with no branches in except to the entry and no branches out except at the exit • average dynamic branch frequency 15% to 25% => 4 to 7 instructions execute between a pair of branches • other problem: instructions in a BB likely depend on each other • To obtain substantial performance enhancements, we must exploit ILP across multiple basic blocks (“trace scheduling”) • Simplest: loop-level parallelism to exploit parallelism among iterations of a loop. E.g., for (j=0; j<1000; j=j+1)        x[j+1] = x[j+1] + y[j+1]; for (i=0; i<1000; i=i+4){        x[I+1] = x[I+1] + y[I+1]; x[I+2] = x[I+2] + y[I+2]; x[I+3] = x[I+3] + y[I+3]; x[I+4] = x[I+4] + y[I+4]; } //{Vector instruction HW can make loops run much faster.} (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  6. Loop-Level Parallelism • Exploit loop-level parallelism to find run-time parallelism by “unrolling loops” either via • dynamic branch prediction by CPU hardware or • static loop unrolling by a compiler (Other ways: vectors & parallelism - covered later) • Determining instruction dependence is critical to Loop Level Parallelism • If two instructions are • “parallel”, they can execute simultaneously in a pipeline of arbitrary depth without causing any stalls (assuming no structural hazards) • dependent, they are not parallel and must be executed in order, although they may often be partially overlapped (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  7. Data Dependence and Hazards • InstrJ is data dependent (aka true dependence) on InstrI: • InstrJ tries to read operand before InstrI writes it • Or InstrJ is data dependent on InstrK which is dependent on InstrI • If two instructions are data dependent, they cannot execute simultaneously or be completely overlapped • Data dependence in instruction sequence  Data dependence in source code  Effect of original data dependence must be preserved • If data dependence causes a hazard in a pipeline, we call it a Read After Write (RAW) hazard – “RAW is real” I: add r1,r2,r3 J: sub r4,r1,r3 (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  8. ILP and Data Dependencies, Hazards • HW/SW must preserve program order: code must give the same results as if instructions were executed sequentially in the original order of the source program • Dependences are a property of programs • The presence of a dependence indicates the potential for a hazard, but the existence of an actual hazard and the length of any stall are properties of the pipeline • Data dependencies are important. They 1) Indicate the possibility of a hazard 2) Determine the order in which results must be calculated 3) Set upper bounds on how much parallelism can possibly be exploited to speedup a program. • HW/SW goal: exploit parallelism by preserving program order only where it affects the outcome of the program (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  9. I: sub r4,r1,r3 J: add r1,r2,r5 I: sub r1,r4,r3 J: add r1,r2,r3 Name Dependence #1: Anti-dependence • Name dependence: occurs when two instructions use the same register or memory location, called a name, but there is no data flow between the instructions using that name. There are 2 versions of name dependence, which may cause WAR and WAW hazards, ifa name such as “r1” is reused: • 1. InstrJ may wrongly write operand r1before InstrI reads it This “anti-dependence” of compiler writers may cause a Write After Read (WAR) hazard in a pipeline. • 2. InstrJ may wrongly write operand r1before InstrI writes it • This “output dependence” of compiler writers may cause a Write After Write (WAW) hazard in a pipeline. • Instructions with a name dependence can execute simultaneously if one name is changed by a compiler or by register-renaming in HW. (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  10. Carefully Violate Control Dependencies • Every instruction is control dependent on some set of branches, and, in general, these control dependencies must be preserved to preserve program order if p1 { S1; }; if p2 { S2; } • S1 is control dependent on proposition p1, and S2 is control dependent on p2, but not on p1. • Control dependence need not always be preserved • Control dependences can be violated by executing instructions that should not have been, if doing so does not affect program results; e.g., “speculative execution” HW throws away results of bad branch guesses. • Two properties critical to program correctness are • exception behavior and • data flow (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  11. Exception Behavior Is Important • Preserving exception behavior  any changes in instruction execution order must not change how exceptions are raised in program ( no new exceptions) • Example: DADDU R2,R3,R4 BEQZ R2,L1 LW R1,-1(R2)L1: • (This code example assumes branches are not delayed) • What is the problem with moving LW before BEQZ? {Array overflow: what if R2=0, so -1+[R2] is out of program memory bounds?} (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  12. Data Flow Of Values Must Be Preserved • Data flow: actual flow of data values from instructions that produce results to those that consume them • branches make flow “dynamic” (since we know details only at runtime); must determine which instruction is supplier of data • Example: DADDU R1,R2,R3BEQZ R4,LDSUBU R1,R5,R6L: …OR R7,R1,R8 • OR input R1depends on which of DADDU or DSUBU? Compilers and HW must preserve data flow during execution (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  13. Outline • ILP • Compiler techniques to increase ILP • Loop Unrolling • Static Branch Prediction • Dynamic Branch Prediction • Overcoming Data Hazards with Dynamic Scheduling • (Start) Tomasulo Algorithm • Conclusion • Reading Assignment: Chapter 2 today, Chapter 3 next. (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  14. Software Techniques - Example • This code adds a scalar to a vector: for (i=1000; i>0; i=i–1) x[i] = x[i] + s; • Assume following latencies for all examples • Ignore delayed branches in these examples Instruction Instruction Latencystalls betweenproducing result using result in cycles in cycles FP ALU op Another FP ALU op 4 3 FP ALU op Store double 3 2 Load double FP ALU op 2 1 Load double Store double 1 0 Integer op Integer op 1 0 (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  15. FP Loop: Where are the Hazards? • for (i=1000; i>0; i=i–1) • x[i] = x[i] + s; • First translate into MIPS code: • -To simplify loop end, assume 8 is lowest address, F2=s, and R1 starts with address for x[1000] Loop: L.D F0,0(R1) ;F0=vector element x[i] ADD.D F4,F0,F2 ;add scalar from F2 = s S.D 0(R1),F4 ;store result back into x[i] DADDUI R1,R1,-8 ;decrement pointer 8Bytes(DblWd) BNEZ R1,Loop ;branch if R1!=zero (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  16. FP Loop Showing Stalls 1 Loop: L.D F0,0(R1) ;F0=vector element 2 stall 3 ADD.D F4,F0,F2 ;add scalar in F2 4 stall 5 stall 6 S.D 0(R1),F4 ;store result 7 DADDUI R1,R1,-8 ;decrement pointer 8Bytes (DW) 8stall;assume cannot forward to branch 9 BNEZ R1,Loop ;branch R1!=zero • Loop every 9 clock cycles. How reorder code to minimize stalls? produce result use result stalls between FP ALU op Other FP ALU op 3FP ALU op Store double 2Load double FP ALU op 1Load double Store double 0Integer op Integer op 0 (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  17. Revised FP Loop Minimizing Stalls Original 9 cycle per loop code 1 Loop: L.D F0,0(R1) ;F0=vector element 2 stall 3 ADD.D F4,F0,F2 ;add scalar in F2 4 stall 5 stall 6 S.D 0(R1),F4 ;store result 7 DADDUI R1,R1,-8 ;decrement pointer 8B 8stall;assume cannot forward to branch 9 BNEZ R1,Loop ;branch R1!=zero 1 Loop: L.D F0,0(R1) 2 DADDUI R1,R1,-8 3 ADD.D F4,F0,F2 4 stall 5 stall 6 S.D 8(R1),F4;altered offset 0=>8 when moved DADDUI 7 BNEZ R1,Loop Loop takes 7 clock cycles, but just 3 for execution (L.D, ADD.D,S.D), 4 for loop overhead; How make faster? Swap DADDUI and S.D; change address offset of S.D produce result use result stalls between FP ALU op Other FP ALU op 3FP ALU op Store double 2Load double FP ALU op 1Load double Store double 0Integer op Integer op 0 (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  18. Unroll Original Loop Four Times (straightforward way gives 7=>6.75 cycles) How rewrite loop to minimize stalls? 1 cycle stall 1 Loop: L.D F0,0(R1) 3 ADD.D F4,F0,F2 6 S.D 0(R1),F4 ;drop DADDUI & BNEZ 7 L.D F6,-8(R1) 9 ADD.D F8,F6,F2 12 S.D -8(R1),F8 ;drop DADDUI & BNEZ 13 L.D F10,-16(R1) 15 ADD.D F12,F10,F2 18 S.D -16(R1),F12 ;drop DADDUI & BNEZ 19 L.D F14,-24(R1) 21 ADD.D F16,F14,F2 24 S.D -24(R1),F16 25 DADDUI R1,R1,#-32 ;alter to 4*8 27 BNEZ R1,LOOP Four loops take 27 clock cycles, or 6.75 per iteration (Assumes R1 is a multiple of 4) 2 cycles stall 1 cycle stall (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  19. Loop Unrolling Detail - Strip Mining • Do not usually know upper bound of loop • Suppose it is n, and we would like to unroll the loop to make k copies of the body • Instead of a single unrolled loop, we generate a pair of consecutive loops: • 1st executes (nmodk) times and has a body that is the original loop {called “strip mining” of a loop} • 2nd is the unrolled body surrounded by an outer loop that iterates (| n/k |) times • For large values of n, most of the execution time will be spent in the | n/k |unrolled loops (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  20. Unrolled Loop That Minimizes (=0) Stalls 1 Loop: L.D F0,0(R1) 2 L.D F6,-8(R1) 3 L.D F10,-16(R1) 4 L.D F14,-24(R1) 5 ADD.D F4,F0,F2 6 ADD.D F8,F6,F2 7 ADD.D F12,F10,F2 8 ADD.D F16,F14,F2 9 S.D 0(R1),F4 10 S.D -8(R1),F8 11 S.D -16(R1),F12 12 DADDUI R1,R1,#-32 13S.D 8(R1),F16 ; 8-32 = -24 14 BNEZ R1,LOOP Four loops take 14 clock cycles, or 3.5 per loop. 1 Loop: L.D F0,0(R1) 3 ADD.D F4,F0,F2 S.D 0(R1),F4 7 L.D F6,-8(R1) 9 ADD.D F8,F6,F2 12 S.D -8(R1),F8 13 L.D F10,-16(R1) 15 ADD.D F12,F10,F2 18 S.D -16(R1),F12 19 L.D F14,-24(R1) 21 ADD.D F16,F14,F2 24 S.D -24(R1),F16 25 DADDUI R1,R1,#-32 ;4*8 27 BNEZ R1,LOOP 27 cycles m means cycle m + 1 stall n means cycle n + 2 stalls (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  21. Five Loop Unrolling Decisions • Requires understanding how one instruction depends on another and how the instructions can be changed or reordered given the dependences: • Determine if loop unrolling can be useful by finding that loop iterations are independent (except for loop maintenance code) • Use different registers to avoid unnecessary constraints forced by using the same registers for different computations • Eliminate the extra test and branch instructions and adjust the loop termination and iteration increment/decrement code • Determine that loads and stores in unrolled loop can be interchanged by observing that loads and stores from different iterations are independent • Transformation requires analyzing memory addresses and finding that no pairs refer to the same address • Schedule (reorder) the code, preserving any dependences needed to yield the same result as the original code (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  22. Three Limits to Loop Unrolling • Decrease in amount of overhead amortized with each extra unrolling • Amdahl’s Law • Growth in code size • For larger loops, size is a concern if it increases the instruction cache miss rate • Register pressure: potential shortfall in registers created by aggressive unrolling and scheduling • If not possible to allocate all live values to registers, code may lose some or all of the advantages of loop unrolling • “Software pipelining” is an older compiler technique to unroll loops systematically. • Loop unrolling reduces the impact of branches on pipelines; another way is branch prediction. (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  23. _ _ Compiler Software-Pipelining of V=S*V Loop Software pipelining structure tolerates the long latencies of FltgPt operations { l.s, mul.s, s.s are single precision (SP) floating-pt. Load, Multiply, Store. } {At start: r1=addr [V(0)], r2=addr[V(last)]+4, f0 = scalar SP fltg multiplier.} Instructions in iteration box are in reverse order, from different iterations. If have separate FltgPt function boxes for L, M, S, can overlap S M L triples. Bg: marks prologue starting iterated code; Ep: marks epilogue to finish code. l.s f2,0(r1) mul.s f4,f0,f2 s.s f4,0(r1) addi r1,r1,4 bne r1,r2,Lp l.s f2,0(r1) mul.s f4,f0,f2 s.s f4,0(r1) addi r1,r1,4 bne r1,r2,Lp l.s f2,0(r1) mul.s f4,f0,f2 s.s f4,0(r1) addi r1,r1,4 bne r1,r2,Lp Bg:addir1,r1,8 l.sf2,-8(r1) mul.sf4,f0,f2 l.sf2,-4(r1) Lp: s.s f4,-8(r1) mul.s f4,f0,f2 l.s f2,0(r1) addi r1,r1,4 bne r1,r2,Lp Ep:s.sf4,-4(r1) mul.sf4,f0,f2 s.sf4,0(r1) I TIME  T 1 2 3 4 5 6 7 8 E 1 LM S R 2 LM S A 3 LM S T 4 LM S I 5 LMS O 6 LMS N  (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  24. Static (Compile-Time) Branch Prediction • An earlier lecture showed scheduling code into a branch delay slot • To reorder (“move”) code around branches, need to predict branch statically when compile • Simplest scheme is to predict a branch as taken • Average misprediction = untaken branch frequency = 34% in SPEC benchmarks • A more accurate scheme predicts branches using profile information collected from earlier runs and modifies predictions based on last run: 11.8% SPEC Integer SPEC Floating Point (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  25. Dynamic (Run-Time) Branch Prediction • Why does prediction work? • Underlying algorithm has regularities • Data that is being operated on has regularities • Instruction sequences have redundancies that are artifacts of way that humans/compilers solve problems • Is dynamic branch prediction better than static prediction? • Seems to be • There are a small number of important branches in programs which have dynamic behavior • Performance = ƒ(accuracy, cost of misprediction) • Branch History Table: Lower bits of PC address index table of 1-bit values • Says whether or not branch taken last time • No address check • Problem: 1-bit BHT will cause two mispredictions per loop, (Average for loops is 9 iterations before exit): • End of loop case, when it exits instead of looping as before • First time through loop on next time through code, when it predicts exit instead of looping (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  26. T Predict Taken Predict Taken T NT NT NT Predict Not Taken Predict Not Taken T T NT Dynamic Branch Prediction With 2 Bits • Solution: 2-bit scheme where change prediction only if get misprediction twice in a row: • Red: stop, not taken • Green: go, taken • Adds hysteresis to decision making process (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  27. Branch History Table (BHT) Accuracy • Mispredict because either: • Make wrong guess for that branch • Got branch history of wrong branch when index the table (same low address bits used for index). • 4096 entry BH table: 7.7% Integer Floating Point (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  28. Correlated Branch Prediction • Idea: record m most recently executed branches as taken or not taken, and use that pattern to select the proper n-bit branch history table • Global Branch History: m-bit shift register keeping Taken/Not_Taken status of last m branches anywhere. • In general, (m,n) predictor means use record of last m global branches to select between 2m local branch history tables, each with n-bit counters • Thus, the old 2-bit BHT is a (0,2) predictor • Each entry (row for given set of address bits) in table has 2mn-bit predictors. (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  29. Correlating Branch Predictors • A (2,2) predictor with 16 sets of four 2-bit predictions • – Behavior of most recent 2 branches selects between four predictions for next branch, updating just that prediction Branch address selects row of entries 4 address bits 2-bits per branch predictor Prediction 2-bit global branch history (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  30. Accuracy of Different Schemes 4096 Entries 2-bit BHT (#=4096) Unlimited Entries 2-bit BHT 1024 Entries (2,2) BHT (#=4096) 20% 18% 16% 14% 12% 11% Frequency of Mispredictions 10% 8% 6% 6% 6% 6% 5% 5% 4% 4% 2% 1% 1% 0% 0% nasa7 li matrix300 tomcatv doducd spice fpppp gcc expresso eqntott 4,096 entries: 2-bits per entry Unlimited entries: 2-bits/entry 1,024 entries (2,2) = better (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  31. Tournament Predictors • Multilevel branch predictor • Use n-bit saturating counter to choose between predictors • Usual choice is between global and local predictors (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  32. Tournament Predictors Tournament predictor using, say, 4K 2-bit counters indexed by local branch address. Chooses between: • Global predictor • 4K entries index by history of last 12 branches (212 = 4K) • Each entry is a standard 2-bit predictor • Local predictor • Local history table: 1024 10-bit entries recording last 10 branches, indexed by branch address • The pattern of the last 10 occurrences of that particular branch used to index table of 1K entries with 3-bit saturating counters (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  33. Comparing Predictors (Fig. 2.8) • Advantage: tournament predictor can select the right predictor for a particular branch • Particularly crucial for integer benchmarks. • A typical tournament predictor will select the global predictor almost 40% of the time for the SPEC Integer benchmarks and less than 15% of the time for the SPEC FP benchmarks 6.8% 2-bit 3.7% Corr, 2.6% Tourn. (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  34. Pentium 4 Misprediction Rate (per 1000 instructions, not per branch) 6% misprediction rate per branch SPECint (19% of INT instructions are branch) 2% misprediction rate per branch SPECfp(5% of FP instructions are branch) SPECint2000 SPECfp2000 (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  35. Branch Target Buffers (BTB) Branch target calculation is costly and stalls the instruction fetch one or more cycles. BTB stores branch PCs and target PCs the same way that caches store addresses and data blocks. The PC of a branch is sent to the BTB When a match is found, the corresponding predicted target PC is returned If the branch is predicted to be Taken, instruction fetch continues at the returned predicted PC Extra logic verifies predicted PC was correct and flushes all incorrectly fetched instructions from pipeline(s) without storing any results

  36. Branch Target Buffers

  37. Dynamic Branch Prediction Summary • Prediction becoming important part of execution • Branch History Table: 2 bits for loop accuracy • Correlation: Recently executed branches correlated with next branch • Either different branches (GA) • Or different executions of same branches (PA) • Tournament predictors take insight to next level, by using multiple predictors • usually one based on global information and one based on local information, and combining them with a selector • In 2006, tournament predictors using  30K bits are in processors like the Power5 and Pentium 4 • Branch Target Buffer: include branch address & prediction (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  38. Outline • ILP • Compiler techniques to increase ILP • Loop Unrolling • Static Branch Prediction • Dynamic Branch Prediction • Overcoming Data Hazards with Dynamic Scheduling • (Start) Tomasulo Algorithm • Conclusion • Reading Assignment: Chapter 2 today, Chapter 3 next week. (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  39. Advantages of Dynamic Scheduling • Dynamic scheduling - hardware rearranges the instruction execution to reduce stalls while maintaining data flow and exception behavior • It handles cases in which dependences were unknown at compile time • it allows the processor to tolerate unpredictable delays such as cache misses, by executing other code while waiting for the miss to resolve • It allows code compiled for one pipeline to run efficiently on a different pipeline • It simplifies the compiler • Hardware speculation, a technique with significant performance advantages, builds on dynamic scheduling (next lecture) (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  40. HW Schemes to Schedule Instructions • Key idea: Allow instructions behind stall to proceedDIVD F0,F2,F4 ADDD F10,F0,F8SUBD F12,F8,F14 • Enables out-of-order execution and allows out-of-order completion(e.g., SUBD before slow DIVD) • In a dynamically scheduled pipeline, all instructions still pass through issue stage in order (in-order issue) • Will distinguish when an instruction begins execution from when it completes execution; between the two times, the instruction is in execution • Note: Dynamic scheduling creates WAR and WAW hazards and makes exception handling harder (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  41. Dynamic Scheduling Step 1 • Simple pipeline had only one stage to check both structural and data hazards: Instruction Decode (ID), also called Instruction Issue • Dynamic scheduling HW splits the ID pipe stage of simple 5-stage pipeline into 2 stages to make a 6-stage pipeline: • Issue—Decode instructions, check for structural hazards • Readoperands—Wait until no data hazards, then read operands (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  42. A Dynamic Algorithm: Tomasulo’s • For IBM 360/91 (before caches!) •  Long memory latency • Goal: High Performance without special compilers • Small number of floating point registers (4 in 360) prevented interesting compiler scheduling of operations • This led Tomasulo to try to figure out how effectively to get more registers — renaming in hardware! • Why Study a 1966 Computer? • The descendants of this have flourished! • Alpha 21264, Pentium 4, AMD Opteron, Power 5, … (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  43. Tomasulo Algorithm • Control & buffers distributed with Function Units (FU) • FU buffers called “reservation stations”; have pending operands • Registers in instructions replaced by values or pointers to reservation stations(RSs); called registerrenaming; • Renaming avoids WAR, WAW hazards • More reservation stations than registers, so can do optimizations compilers cannot do without access to the additional internal registers, the reservation stations. • Results from RSs as leave each FU sent to waiting RSs, not through registers, but over a Common Data Busthat broadcasts results to all FUs and their waiting RSs • Avoids RAW hazards by executing an instruction only when its operands are available • Load and Stores treated as FUs with RSs as well • Integer instructions can go past branches (predict taken), allowing FP ops beyond basic block in FP queue (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  44. Tomasulo Organization FP Registers From Mem FP Ops Queue Load Buffers Load1 Load2 Load3 Load4 Load5 Load6 Store Buffers Add1 Add2 Add3 Mult1 Mult2 Reservation Stations To Mem FP adders FP multipliers Common Data Bus (CDB) (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  45. Three Stages of Tomasulo Algorithm 1.Issue—get instruction from FP Op Queue If reservation station free (no structural hazard), control issues instr & sends operands (renames registers). 2.Execute—operate on operands (EX) When both operands ready, start to execute; if not ready, watch Common Data Bus for result 3.Writeresult—finish execution (WB) Write on Common Data Bus to all awaiting units; mark reservation station available • Normal data bus: data + destination (“go to” bus) • Common data bus: data + source (“come from” bus) • 64 bits of data + 4 bits of Functional Unit source address • Write if matches expected Functional Unit (produces result) • Does the broadcast • Latencies for instructions in example slides that follow: After start EX: 2 clocks for LD; 3 for Fl .pt. +,-; 10 for * ; 40 for /. (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  46. Reservation Station Components Op: Operation to perform in the unit (e.g., + or –) Vj, Vk: Value of source operands for Op • Each store buffer has a V field, for the result to be stored Qj, Qk: Reservation stations producing source registers (value to be written) • Note: Qj,Qk=0 => ready • Store buffers have only one Qi for RS producing result Busy: Indicates reservation station or FU is busy Register resultstatus—Indicates which functional unit will write each register, if one exists. Blank when no pending instructions will write that register. (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  47. Instruction stream 3 Load/Buffers FU count down 3 FP Adder R.S. 2 FP Mult R.S. Clock cycle counter Tomasulo Example (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  48. Tomasulo Example Cycle 1 (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  49. Tomasulo Example Cycle 2 Note: Can have multiple loads outstanding (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

  50. Tomasulo Example Cycle 3 • Note: registers names are removed (“renamed”) in Reservation Stations; MULTD issued; (2 clks for LD; 3 FP +,-; 10 for * ; 40 for /) • Load1 completing; what is waiting for Load1? (quiz was 2/22, QuizAns 3/3) CSE502-S10, Lec 08+9+10-ILP

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