October 10, 2000

1. October 10, 2000 1

2. October 10, 2000 2 USB 2.0 Host Controllers(EHCI Specification) John S. Howard Intel Corporation

3. October 10, 2000 3 Agenda Project Overview Key Features Overview USB 2.0 Host Controller Architecture EHCI HC Interface Architecture EHCI HC Data Structures Operational Models (Overview/Examples) Host Controller Compliance Program Summary

4. October 10, 2000 4 Project Overview Intel developed specification with contributionsfrom NEC, Lucent, Philips, Compaq and Microsoft Licensees** can also contribute to specification Enhanced Host Controller Specification for USB Defines the architecture for a USB 2.0 capable host controller, and Defines register (hardware/software) interfacefor a high-speed capable host controller

5. October 10, 2000 5 Project Overview Public revisions will be available soon Each revision comes with a license agreement Revision 0.95 will be the first public release License agreement provides reciprocal royalty free license to manufacture compliant discrete USB 2.0 host controllers based on this specification Revision 1.0 is the final specification License agreement provides reciprocal royalty free license to manufacture compliant USB 2.0 host controllers based on this specification

6. October 10, 2000 6 USB 2.0 Host Controller Architecture Multi-function Controller delivers 3 port speeds Simplifies High-speed Host Controller Optimize for high-speed functionality Reuses USB 1.1 Host Controller Designs (drop-in) USB ports work independent of high-speed capable software

7. October 10, 2000 7 USB 2.0 Host Controller Architecture: Port Routing Rules Ports owned by Companion controllers when HS HC software is absent When HS HC Software is present, it “configures” High-Speed HC then: Retains ownership for high-speed devices Releases individual port ownership if attached device is not high speed Routing Logic signals a disconnect on HS HC and a connect on Companion HC Ownership returns to HS HC on a disconnect event

8. October 10, 2000 8 EHCI Interface Architecture (Overview) PCI Configuration Registers PCI Class Codes Memory space base address for register space Power Management Interface Memory-based I/O Registers Capability Registers Implementation-specific, read-only parameters for driver Operational Registers Host controller management List Management Port control registers Shared Memory Work Lists Two schedule Lists (periodic, asynchronous) Queuing data structures Used for transfer types guarantee delivery Different data structures used for isochronous Different data structures for high- and full-speed Optimized for streaming isochronous data No support for retriesPCI Configuration Registers PCI Class Codes Memory space base address for register space Power Management Interface Memory-based I/O Registers Capability Registers Implementation-specific, read-only parameters for driver Operational Registers Host controller management List Management Port control registers Shared Memory Work Lists Two schedule Lists (periodic, asynchronous) Queuing data structures Used for transfer types guarantee delivery Different data structures used for isochronous Different data structures for high- and full-speed Optimized for streaming isochronous data No support for retries

9. October 10, 2000 9 Operational I/O Registers Command/Configuration Management of HC, schedules on/off, etc. Status Interrupt Management Schedule Management Periodic Base Pointer Frame Index Asynchronous List Pointer Port Status and Control

10. October 10, 2000 10 Agenda Project Overview Key Features Overview USB 2.0 Host Controller Architecture EHCI HC Interface Architecture EHCI HC Data Structures Operational Models (Overview/Examples) Host Controller Compliance Program Summary

11. October 10, 2000 11 EHCI Data Structures Five (5) basic data structures (schedule objects) Queuing Data Structure (2) High-speed isochronous (1) Full-speed isochronous (1) Frame List (1) Used to build construct Periodic and Asynchronous Schedules All data structures support simple data buffer scatter/gather

12. October 10, 2000 12 Queuing Data StructuresOverview Queues are used for ALL Non-Isochronous transfers Uses 2 data structures: qHead and a qElement 1 queue per endpoint Each queue element (transaction descriptor)describes a buffer (1 to many transactions) Up to 20 Kbytes per transaction descriptor 16Kbytes with worst-case buffer alignment No Hardware/software sync required to add work to a queue Architecture optimized to provide efficient memory accesses Block, burst accesses Efficient, cache execution model

13. October 10, 2000 13 HS Isochronous Data Structure Overview HS Isochronous use isochronous Transfer Descriptors (iTDs) Linked into periodic schedule (made ‘reachable’ in the appropriate frames) Time-oriented data structure “Frame number” encoded in topology of list No hardware (micro)-frame arithmetic required Position of work item in periodic list determines whenit will be “seen” and executed by the host controller 8 transaction descriptions per iTD Supports High-bandwidth Supports up to 28K bytes per iTD Requires multiple iTDs to maintain HS isochronous data stream

14. October 10, 2000 14 FS Isochronous Data Structure Overview FS Isochronous uses split isochronous Transfer Descriptors (siTDs) Similar usage and behavioral model as iTDs, except: Will only use split transactions 1 FS transaction per siTD Linked in one siTD per Frame Supports one page boundary Appropriate mechanisms to care and feed isoch split transaction

15. October 10, 2000 15 Periodic Frame List Array of schedule object pointers Represents a rolling window of time Each location is base pointer for one frame’s worth of work (8 micro-frames) Frame work for establishing time oriented reachability HC builds a Periodic Frame list address from: Periodic frame list base address Frame Index Register [12:3] increments once each frame (1ms)

16. October 10, 2000 16 Agenda Project Overview Key Features Overview USB 2.0 Host Controller Architecture EHCI HC Interface Architecture EHCI HC Data Structures Operational Models (Overview/Examples) Host Controller Compliance Program Summary

17. October 10, 2000 17 EHCI Operational Models Asynchronous Schedule Overview Queuing example operation Periodic Schedule Overview HS Isochronous HS Interrupt Asynchronous split transactions Periodic split transactions

18. October 10, 2000 18 Asynchronous Schedule Overview Schedule includes only Queue Heads Organized in simple, circular list Manages HS/FS/LS asynchronous endpoints Yields Round-Robin Service Order Supports FS/LS asynchronous

19. October 10, 2000 19 Queuing Example Operation

20. October 10, 2000 20 Periodic Schedule Overview Periodic Frame List is the base Size is optionally programmable Objects linked so are ‘reachable’ at the correct time Schedule graph includes: Queue Heads for Interrupt HS Isochronous, FS Isochronous

21. October 10, 2000 21 HS Isochronous Example Operation

22. October 10, 2000 22 HS Interrupt Uses queuing data structures No change to behavioral model Linked into periodic schedule (made ‘reachable’ in the appropriate frames) HS poll rates are micro-frames Embedded bit-mask in qHead describes micro-frame pattern Simple mechanism to support high-bandwidth

23. October 10, 2000 23 Asynchronous Split Transactions Micro-machine extension to the HS queue execution model HS transfer advancement occurs when HS transaction is complete FS/LS transfer advancement occurs when start-split and complete splits are complete Endpoint speed encoding directs HC to use split protocol All other behavior same as HS asynchronous

24. October 10, 2000 24 Periodic Split Transactions Used to service data streams through TT periodic pipelines Requirement on HC is to: Execute starts and completes when they need to occur Each endpoint data structure contains: Masks for Starts/Completes Micro-state to track progress (to detect lost data, etc.) Projection of core-spec bus frame boundaries into the host schedule created many scheduling boundary conditions, so…

25. October 10, 2000 25 Mapping Bus Frames to Host Frames In order to simplify host for TT pipeline support: Host view of frame boundaries is shifted one micro-frame

26. October 10, 2000 26 FS/LS Interrupt INExample Operation

27. October 10, 2000 27 FS Isochronous INExample Operation

28. October 10, 2000 28 Agenda Project Overview Key Features Overview USB 2.0 Host Controller Architecture EHCI HC Interface Architecture EHCI HC Data Structures Operational Models (Overview/Examples) Host Controller Compliance Program Summary

29. October 10, 2000 29 EHCI Compliance Program

30. October 10, 2000 30 EHCI Compliance Program EHCI-specific compliance software under development at Intel Special compliance devices(high-speed and full/low speed) Special-purpose application and driver for controlled testingand analysis Interface Functional Testing Device Interoperability USB 2.0 protocol andtransfer extensions System Interaction Etcetera, …

31. October 10, 2000 31 EHCI Compliance Program Test Availability HC compliance test will be available from Intel Method of distribution (to be defined) Alpha-level tools available in Q1 2001 Beta-level tools available in Q2 2001 Production release available with release of 1.0 EHCI host controller specification in Q3

32. October 10, 2000 32 Summary Low-risk Introduction All ports are HS/FS/LS Capable Legacy (non-high-speed aware) software just works Re-use of 1.1 controllers simplifies high-speed controller Interface optimized for good memoryaccess efficiency Reasonable tradeoff of hardware/software complexity

33. October 10, 2000 33 Summary Host controller compliance program Alpha release Q1, 2001 Beta release Q2, 2001 Final with 1.0 EHCI Specification Specification Revisions available: Revision 0.95 for discrete HC Q3 2000 Revision 1.0 in 2001 Gating item is validation of integrated host controller