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AubieSat-1 PDR Communications

AubieSat-1 PDR Communications. 12/06/08. Schedule Review. Things Left to be Done. Things Done. The primary transceiver Orcad Schematics updated for receiver and LNA optimization First Revision of PCB Populated and tested Second Revision of PCB Currently being designed

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AubieSat-1 PDR Communications

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  1. AubieSat-1 PDRCommunications 12/06/08

  2. Schedule Review Things Left to be Done Things Done • The primary transceiver • Orcad Schematics updated for receiver and LNA optimization • First Revision of PCB • Populated and tested • Second Revision of PCB • Currently being designed • Pin header assignments finalized • Decoder Lines assignments finalized • The primary transceiver • Continue PCB Revisions • Fine-Tune Component Values • Increase Gain of transmitter by ~ 3dB

  3. Schedule Review (2) Things Left to be Done Things Done • The secondary receiver • Orcad Schematics updated for receiver and LNA optimization • Second Revision of PCB • Populated and Tested • Third Revision of PCB • Designed and ready to order • LNA • Simulated, populated and tested • Experimental Results agree with Simulation Results • The secondary receiver • Fine-Tune Component Values for every newly populated PCB • BER testing for Second Revision of populated PCB • Populate 3rd Revision of PCB and perform all testing defined in test plan document

  4. Schedule Review (3)‏ Things Done Things Left to be Done • Frequency Spectrum of FSK Modulated Carrier • Matlab simulation • Experimental measurements • FSK base-band signal simulation with Matlab • Link Budget Analysis is developed and updated • All links closed successfully • Link budget must continually be updated as COMM 1&2 further define specifications from testing

  5. Schedule Review (4)‏ Things Done Things Left to be Done • The Antenna Subsystem • Secure connection between antenna and ADM board- (use copper crimps and silver solder) • Antenna length determined- (.686meters) • ADM/Antenna board layout • Matching network design- (LC circuit) • PCB board designed and populated • The Antenna Subsystem • Antenna performance must be tested with PCB matching network implemented • Continue PCB revisions: • include deployment switches • reduce the trace lengths from antenna • use 50 ohm micro-strip where traces are needed.

  6. Overall Functional Diagram Primary Receiver Received signal USRT TX C&DH TNC FSK AX-25 Antenna Switch Primary Transmitter USRT RX Transmitted signal Primary Antenna Secondary Command Lines 1-4 Ground Station Antenna Primary Ground Station Antenna Switch & AMP Secondary RX Secondary Ground Station Second Antenna

  7. Glossary of Terms • LNA-Low Noise Amplifier • LNA increases Secondary Communications Receiver sensitivity • Cascode Amplifier • two-stage amplifier composed of a trans-conductance amplifier followed by a current buffer • BER-Bit Error Rate • Number of Bit Errors that occur over a specified time [Bits/sec] • PSRB-Pseudo Random Binary Sequence • Baseband signal to be frequency shift key (FSK) modulated. • S-parameters or Scattering Parameters • Parameters used to measure the Transmission and Reflection properties of a device or circuit • MPA - Medium Power Amplifier • On board power amplifier used to increase the very low power signal to a recognizable level

  8. Secondary Receiver (Sam and Mark)

  9. Functional Diagram for Secondary Receiver Secondary Antenna Melexis Reciever TH71102 Squelch Circuit Holtec Decoder HT12D LNA 2nd RX Lines (1-4)‏

  10. Secondary Comm Schematics TH71102 RECEIVER LNA Decoder And Squelch Circuit

  11. Secondary Receiver PCB • Revision #3 • SMA connector • Low Noise Amplifier (LNA) • Melexis Receiver IC (TH71102)‏ • Squelch Circuit • Holtec Decoder

  12. Current Performance • Second Revision of PCB: • Receiver able to interpret signal attenuated by: • -108dB with manually tuned variable capacitors • -100dB with fixed value capacitors • LNA has a gain of 14dB • Have populated a single PCB with both designs and have observed decreased performance in the receiver

  13. LNA Simulation in ADS BF1212 is two FETs in cascode configuration

  14. S-Parameter Measurements

  15. S-Parameter Measurements

  16. BER Testing on TH71102 Eval Board • BER Testing to choose component values need to close link budget. • Bandwidth selection • Needed for frequency allocations • Choose frequency deviation

  17. Frequency Shift Keying Modulation (Matlab)‏ • Matlab code to generate base-band PRBS • Binary Signal • 0 corresponds to F1 • 1 corresponds to F2 • Transitions generate spectral noise.

  18. F0 Fc F1 FSK Spectrum Simulation (Matlab)‏ • Base-Band Input • Pseudo Random Binary Sequence (PRBS)‏ • Design Variables: • ∆f (frequency Deviation)‏ • fc (Carrier Frequency)‏ • Bit Rate • 1200BPS for Primary • 4500BPS for Secondary

  19. FSK Spectrum Measurements • Base-Band Input • Pseudo Random Binary Sequence (PRBS)‏ • Design Variables: • ∆f (frequency Deviation)‏ • fc (Carrier Frequency)‏ • Bit Rate • 1200BPS for Primary • 4500BPS for Secondary *This measurement taken by John Klingelhoeffer

  20. Receiver Components (John)

  21. Three Receivers in the AubieSat / Ground Station system • Primary and Secondary Receivers on Satellite • Receiver on Ground Station (GS) • Slight differences amongst these receivers, but they are essentially the same • All three use TH71102 from Melexis • Primary and GS: 1.2kbps, ~437MHz • Secondary: 4.5kbps, ~437MHz

  22. Pi Network Matching • Allows impedance matching with band-pass filtering • Used in multiple times in receiver • MATLAB script developed for quick computation Conceptual Diagram Pi Network simulation for 10.7MHz Ceramic filter with 600 ohm input impedance

  23. IN_LNA Matching Network is matched; Zc = 5Ω However, 9.1nH not a obtainable value (as far as I could find) 50Ω 26Ω || 2pF Original Schematic Network is matched; Zc = 3.65Ω All components obtainable Revised Version* *Schematics not yet officially revised

  24. Experimental Matching • Used smith chart to do impedance matching • Used variable capacitor for C42 to optimize performance

  25. OUT_MIX2 Matching For 330Ω Input/Output impedance filters 2200Ω 330Ω Original Schematic For 600Ω Input/Output impedance filters (Zc = 2.5 ohms)

  26. Double-Tuned Band-Pass Filter • Combined with the helical filter, provides image rejection (~42 dB in current configuration) • Tuning is very sensitive • Very high Q (approx. 100) • Elsie, PSPICE simulations showed that a value of 0.36pf for C55 is not optimal • Alternative values for all components tried • C55 optimally should be 0.6pf, value unavailable; new value 0.5pf

  27. PSPICE Model and Frequency Response of Double-Tuned Band-Pass Filter

  28. Experimental BPF Debugging • Omitted 2nd “tank” circuit • Observed an immediate increase in performance • Tuned C27 with variable capacitor to optimize performance

  29. Bandwidth Considerations

  30. FSK Detection with the Internal Comparator • OUTP and OUTN output voltage dependent on frequency of received signal • OAP and OAN op-amp (comparator) inputs • Large number of slots in board allocated for a choice in LPF configurations 100k – 300k Ω

  31. Suggested Solution (for secondary receiver): OAP OUTP OUT_OA OA OAN

  32. Where do these values come from? C1:? • OUTP resistance = 100k – 300k Ω • Along with the output resistance of OUTP, C1 forms an RC-series LPF • Square waves present on OUTP can be broken up into Fourier Series components at • 1, 3, 5, 7, etc. times the fundamental frequency • LPF cuts off at 5 times fundamental frequency • Fundamental frequency = 0.5*bit rate • Pole for an RC series LPF is at sCR = 1, so: • where Fb = bit rate • Contribution impedance in the rest of the circuit high enough to not affect this LPF performance much

  33. Where do these values come from? (page 2) C2:? • We want the voltage on OAP to be higher than on OAN during “1”s and lower than on OAN during “0”s • Rate that voltage changes depends on RC time constant • R picked somewhat arbitrarily to be 330k (needed to be a high value) • V = Vi*e^(-t/RC) • After t = 5RC, capacitor is usually considered fully discharged • Worst case: Long consecutive string of 1’s or 0’s • Capacitor would be charging or discharging entire period • Assumption: Longest string of the same digit = 8 identical bits in a row • To allow margin then, set 3RC = 8*(bit period), which leads to: • where Fb = bit rate • R = 330k Ω

  34. FSK Detection Issue • Was quickly discovered in testing that OUTP needs to have a resistive load on it • Solution below was implemented, similar to eval board • However, extra resistor reduces cutoff of higher frequencies

  35. Squelching Circuit • Receiver continuously outputs a random logic state if no signal received • Squelching circuit looks at Received Signal Strength Indicator (RSSI) voltage • Bars data from getting to decoder if RSSI voltage is too low • Original circuit did not contain AND gate; AND gate necessary to allow/disallow data transmission

  36. Squelching Circuit (Continued) • RSSI voltage for minimum power, decodable signal poorly defined on data sheet • Experiments in lab seem to indicate RSSI is about ~0.5V for the minimum decodable signal • Resistors chosen to provide a hysteresis effect with a turn-on voltage of 0.50V and turn-off voltage of 0.42V. • A concern is that RSSI voltage may vary from chip to chip or based on content of data stream • Additional testing required!

  37. Transmitter & TNC (Joey)

  38. Current Design State • Primary Communication System • Printed Circuit Board built for: • Ground Station version • Onboard version • Secondary Communication System • Printed Circuit Board built for: • Ground Station version • TNC • Transmitting Data

  39. Large Power Amplifier Encoder Transmitter MPA

  40. Secondary Transmitter Schematics

  41. Ground Station Transmitter PCB Layout

  42. Transceiver Functional Diagram Power control line (analog)‏ PSEL Transmitter Melexis TH72011 NEC MPA and LFP Assembly I2C Interface Integrated Circuit NXP PCA9554 I2C Bus Data, Serial Transmit Ω Ω To C&DH processor To SCR Decoder; 0 = Allow 1 = Inhibit Micrel High Side Switch MIC94062 MPA Power +5V 2x NC7WZ07 Primary Antenna To SCR Decoder; 0 = Normal 1 = CW BCN ENTX 1/6 CD74HC04 1/6 CD74HC04 Transmit =1 Receive = 0 K-ID2 CW ID AND TIMER KEY 1 = Allow 0 = Inhibit AND PTT NC7S08 TRIGGER NEC uPG2010TB GaAs T/R Switch Transmit = 1 Receive = 0 TNC-X PIC 16F628A TX Data Mode Control Line: Transmit [H]; Receive [L] Vcont OR RB0 PTT 1/6 CD74HC04 1/6 CD74HC04 NC7SZ332 To C&DH processor Receiver Melexis TH71102 LNA & HBPF Assembly Transmit = 0 Receive = 1 MX614 M0, M1 Mode control lines not connected Squelch Status ENRX Micrel High Side Switch MIC94062 RX Data LNA Power +5V Data, Serial Receive AUdacious Transceiver board functional block diagram Rev 3 16 SEP 08 J. H. Klingelhoeffer

  43. Transceiver Schematics

  44. Transceiver Schematics(2)‏

  45. Transceiver PCB Layout

  46. Transmitter Output Power 7.69dBm 2.12dBm -3.51dBm -12.95dBm

  47. Transmitter Matching Elements • Transmitter normal output is 23 ohm • This needs to be matched to 50 ohm to be compatible with the Comm system • The difference is staggering 7.69dBm -8.81dBm

  48. Comm1 - TNC • Data can pass through from TNC to TNC, by bypassing the transmitter and receiver circuit. PC 1 PC 2 GPIO 1 GPIO 2 TNC 1 TX TNC 2 RX

  49. Comm1 – Morse Code • Achieved by shift power levels • Transmitter Power 1 at +7.6197 dbm • Transmitter Power 4 at -63dbm • Indistinguishable from noise

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