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5/28/03 Minute Paper

5/28/03 Minute Paper. Do we get to use a note card or cheat sheet again? and calculator? Do we have to know electrical safety for the test?. Digital Circuit Review: Combinational Logic. Logic operation Real problem to truth table Karnaugh Map: Box “1” or box “0” Largest supercell possible

angelica-farley
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5/28/03 Minute Paper

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  1. 5/28/03 Minute Paper • Do we get to use a note card or cheat sheet again? and calculator? • Do we have to know electrical safety for the test?

  2. Digital Circuit Review: Combinational Logic • Logic operation • Real problem to truth table • Karnaugh Map: • Box “1” or box “0” • Largest supercell possible • 2n ones or zeros in each supercell • Edges of Karnaugh map are connected • Finish all ones or zeros • Doesn’t matter (“d” or “x”) can be considered as either “1” or “0”.

  3. Digital Circuit Review: Sequential Logic • Flip Flips • Timing diagram • When CLK signal arrives (rising edge or falling edge), FF will have outputs (Q and Q’) depending on the input (ex. D, or J, K). At this stage, ignore combinational logic if there exist in the circuit. • After finishing the output (Q and Q’), then work on the combinational logic, which typically determines the inputs (ex. D, or J, K) which will determine the output (Q and Q’) at next CLK signal • Sequential circuit design: State Map • Construct a state map. • Convert the state map to truth map. Note: have to include all combination. Ex. If there are three outputs, Q0, Q1, and Q2, then there are 8 states (combinations) that have to be listed. Some of them may be listed as “d”. • Prepare the inputs such that the outputs (Q0, Q1, and Q2) at next state will follow the state map. • Convert the truth map to Karnaugh map: the inputs of FF (ex, D, or J, K) is the results in Karnuagh map, i.e. the value of the inputs of FF goes into cells. The outputs of FF is the inputs in the Karnaugh map.

  4. 5V Example 1 • Ch. 13.20, three votes, two yes, pass, green light on, otherwise, fail, red light on. F=AB+BC+AC

  5. 11 01 10 Example 2: timing diagram Construct the timing diagrams below to ascertain the state diagram for both E=1 and E=0. Complete the state diagram to show the behavior of this 2-bit counter for E disabled.    Complete the state diagram to show the behavior of this 2-bit counter for E enabled. 00 01 10

  6. Example 3: Sequential logic design Using D-type flip-flops and a single two-input logic gate, design a 2-bit state counter that will execute the sequence in this state diagram: Show the type of gate and the connections to the flip-flops needed for this counter on the schematic below: Karnaugh Map for D2 D2=Q1’Q2’

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