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EE (CE) 6304 Computer Architecture Lecture #17 (11/27/17)

EE (CE) 6304 Computer Architecture Lecture #17 (11/27/17). Yiorgos Makris Professor Department of Electrical Engineering University of Texas at Dallas. Course Web-site: http://www.utdallas.edu/~gxm112130/EE6304FA17. Another Approach: Multithreaded Execution.

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EE (CE) 6304 Computer Architecture Lecture #17 (11/27/17)

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  1. EE (CE) 6304 Computer ArchitectureLecture #17(11/27/17) Yiorgos Makris Professor Department of Electrical Engineering University of Texas at Dallas Course Web-site: http://www.utdallas.edu/~gxm112130/EE6304FA17

  2. Another Approach: Multithreaded Execution • Multithreading: multiple threads to share the functional units of 1 processor via overlapping • processor must duplicate independent state of each thread e.g., a separate copy of register file, a separate PC, and for running independent programs, a separate page table • memory shared through the virtual memory mechanisms, which already support multiple processes • HW for fast thread switch; much faster than full process switch  100s to 1000s of clocks • When switch? • Alternate instruction per thread (fine grain) • When a thread is stalled, perhaps for a cache miss, another thread can be executed (coarse grain)

  3. Fine-Grained Multithreading • Switches between threads on each instruction, causing the execution of multiples threads to be interleaved • Usually done in a round-robin fashion, skipping any stalled threads • CPU must be able to switch threads every clock • Advantage is it can hide both short and long stalls, since instructions from other threads executed when one thread stalls • Disadvantage is it slows down execution of individual threads, since a thread ready to execute without stalls will be delayed by instructions from other threads • Used on Sun’s Niagara (will see later)

  4. Coarse-Grained Multithreading • Switches threads only on costly stalls, such as L2 cache misses • Advantages • Relieves need to have very fast thread-switching • Doesn’t slow down thread, since instructions from other threads issued only when the thread encounters a costly stall • Disadvantage is hard to overcome throughput losses from shorter stalls, due to pipeline start-up costs • Since CPU issues instructions from 1 thread, when a stall occurs, the pipeline must be emptied or frozen • New thread must fill pipeline before instructions can complete • Because of this start-up overhead, coarse-grained multithreading is better for reducing penalty of high cost stalls, where pipeline refill << stall time • Used in IBM AS/400, Alewife

  5. For most apps:most execution units lie idle For an 8-way superscalar. From: Tullsen, Eggers, and Levy, “Simultaneous Multithreading: Maximizing On-chip Parallelism, ISCA 1995.

  6. Do both ILP and TLP? • TLP and ILP exploit two different kinds of parallel structure in a program • Could a processor oriented at ILP to exploit TLP? • functional units are often idle in data path designed for ILP because of either stalls or dependences in the code • Could the TLP be used as a source of independent instructions that might keep the processor busy during stalls? • Could TLP be used to employ the functional units that would otherwise lie idle when insufficient ILP exists?

  7. Simultaneous Multi-threading ... One thread, 8 units Two threads, 8 units Cycle M M FX FX FP FP BR CC Cycle M M FX FX FP FP BR CC M = Load/Store, FX = Fixed Point, FP = Floating Point, BR = Branch, CC = Condition Codes

  8. Simultaneous Multithreading (SMT) • Simultaneous multithreading (SMT): insight that dynamically scheduled processor already has many HW mechanisms to support multithreading • Large set of virtual registers that can be used to hold the register sets of independent threads • Register renaming provides unique register identifiers, so instructions from multiple threads can be mixed in datapath without confusing sources and destinations across threads • Out-of-order completion allows the threads to execute out of order, and get better utilization of the HW • Just adding a per thread renaming table and keeping separate PCs • Independent commitment can be supported by logically keeping a separate reorder buffer for each thread Source: Micrprocessor Report, December 6, 1999 “Compaq Chooses SMT for Alpha”

  9. Multithreaded Categories Simultaneous Multithreading Multiprocessing Superscalar Fine-Grained Coarse-Grained Time (processor cycle) Thread 1 Thread 3 Thread 5 Thread 2 Thread 4 Idle slot

  10. Design Challenges in SMT • Since SMT makes sense only with fine-grained implementation, impact of fine-grained scheduling on single thread performance? • A preferred thread approach sacrifices neither throughput nor single-thread performance? • Unfortunately, with a preferred thread, the processor is likely to sacrifice some throughput, when preferred thread stalls • Larger register file needed to hold multiple contexts • Clock cycle time, especially in: • Instruction issue - more candidate instructions need to be considered • Instruction completion - choosing which instructions to commit may be challenging • Ensuring that cache and TLB conflicts generated by SMT do not degrade performance

  11. Single-threaded predecessor to Power 5. 8 execution units in out-of-order engine, each may issue an instruction each cycle. Power 4

  12. Power 4 2 commits (architected register sets) Power 5 2 fetch (PC),2 initial decodes

  13. Power 5 data flow ... Why only 2 threads? With 4, one of the shared resources (physical registers, cache, memory bandwidth) would be prone to bottleneck

  14. Power 5 thread performance ... Relative priority of each thread controllable in hardware. For balanced operation, both threads run slower than if they “owned” the machine.

  15. Changes in Power 5 to support SMT • Increased associativity of L1 instruction cache and the instruction address translation buffers • Added per thread load and store queues • Increased size of the L2 (1.92 vs. 1.44 MB) and L3 caches • Added separate instruction prefetch and buffering per thread • Increased the number of virtual registers from 152 to 240 • Increased the size of several issue queues • The Power5 core is about 24% larger than the Power4 core because of the addition of SMT support

  16. Initial Performance of SMT • Pentium 4 Extreme SMT yields 1.01 speedup for SPECint_rate benchmark and 1.07 for SPECfp_rate • Pentium 4 is dual threaded SMT • SPECRate requires that each SPEC benchmark be run against a vendor-selected number of copies of the same benchmark • Running on Pentium 4 each of 26 SPEC benchmarks paired with every other (262 runs) speed-ups from 0.90 to 1.58; average was 1.20 • Power 5, 8 processor server 1.23 faster for SPECint_rate with SMT, 1.16 faster for SPECfp_rate • Power 5 running 2 copies of each app speedup between 0.89 and 1.41 • Most gained some • Fl.Pt. apps had most cache conflicts and least gains

  17. Head to Head ILP competition

  18. Performance on SPECint2000

  19. Performance on SPECfp2000

  20. Normalized Performance: Efficiency

  21. No Silver Bullet for ILP • No obvious over all leader in performance • The AMD Athlon leads on SPECInt performance followed by the Pentium 4, Itanium 2, and Power5 • Itanium 2 and Power5, which perform similarly on SPECFP, clearly dominate the Athlon and Pentium 4 on SPECFP • Itanium 2 is the most inefficient processor both for Fl. Pt. and integer code for all but one efficiency measure (SPECFP/Watt) • Athlon and Pentium 4 both make good use of transistors and area in terms of efficiency, • IBM Power5 is the most effective user of energy on SPECFP and essentially tied on SPECINT

  22. Limits to ILP • Doubling issue rates above today’s 3-6 instructions per clock, say to 6 to 12 instructions, probably requires a processor to • issue 3 or 4 data memory accesses per cycle, • resolve 2 or 3 branches per cycle, • rename and access more than 20 registers per cycle, and • fetch 12 to 24 instructions per cycle. • The complexities of implementing these capabilities is likely to mean sacrifices in the maximum clock rate • E.g, widest issue processor is the Itanium 2, but it also has the slowest clock rate, despite the fact that it consumes the most power!

  23. Limits to ILP • Most techniques for increasing performance increase power consumption • The key question is whether a technique is energy efficient: does it increase power consumption faster than it increases performance? • Multiple issue processors techniques all are energy inefficient: • Issuing multiple instructions incurs some overhead in logic that grows faster than the issue rate grows • Growing gap between peak issue rates and sustained performance • Number of transistors switching = f(peak issue rate), and performance = f( sustained rate), growing gap between peak and sustained performance  increasing energy per unit of performance

  24. Commentary • Itanium architecture does not represent a significant breakthrough in scaling ILP or in avoiding the problems of complexity and power consumption • Instead of pursuing more ILP, architects are increasingly focusing on TLP implemented with single-chip multiprocessors • In 2000, IBM announced the 1st commercial single-chip, general-purpose multiprocessor, the Power4, which contains 2 Power3 processors and an integrated L2 cache • Since then, Sun Microsystems, AMD, and Intel have switch to a focus on single-chip multiprocessors rather than more aggressive uniprocessors. • Right balance of ILP and TLP is unclear today • Perhaps right choice for server market, which can exploit more TLP, may differ from desktop, where single-thread performance may continue to be a primary requirement

  25. And in conclusion … • Limits to ILP (power efficiency, compilers, dependencies …) seem to limit to 3 to 6 issue for practical options • Explicitly parallel (Data level parallelism or Thread level parallelism) is next step to performance • Coarse grain vs. Fine grained multithreading • Only on big stall vs. every clock cycle • Simultaneous Multithreading if fine grained multithreading based on OOO superscalar microarchitecture • Instead of replicating registers, reuse rename registers

  26. Supercomputers Definition of a supercomputer: • Fastest machine in world at given task • A device to turn a compute-bound problem into an I/O bound problem • Any machine costing $30M+ • Any machine designed by Seymour Cray CDC6600 (Cray, 1964) regarded as first supercomputer

  27. Vector Supercomputers Epitomized by Cray-1, 1976: Scalar Unit + Vector Extensions • Load/Store Architecture • Vector Registers • Vector Instructions • Hardwired Control • Highly Pipelined Functional Units • Interleaved Memory System • No Data Caches • No Virtual Memory

  28. Cray-1 (1976)

  29. V0 V. Length V. Mask V1 V2 V3 V4 S0 V5 S1 V6 S2 V7 S3 S4 S5 S6 S7 Int Add A0 A1 Int Logic A2 A3 Int Shift A4 A5 Pop Cnt A6 A7 CIP Cray-1 (1976) Vi Vj 64 Element Vector Registers Vk Single Port Memory 16 banks of 64-bit words + 8-bit SECDED 80MW/sec data load/store 320MW/sec instruction buffer refill FP Add Sj FP Mul ( (Ah) + j k m ) Sk FP Recip Si 64 T Regs (A0) Si Tjk ( (Ah) + j k m ) Aj Ai 64 B Regs (A0) Ak Addr Add Bjk Ai Addr Mul NIP 64-bitx16 LIP 4 Instruction Buffers memory bank cycle 50 ns processor cycle 12.5 ns (80MHz)

  30. Scalar Registers Vector Registers r15 v15 r0 v0 [0] [1] [2] [VLRMAX-1] Vector Length Register VLR v1 Vector Arithmetic Instructions ADDV v3, v1, v2 v2 v3 + + + + + + [0] [1] [VLR-1] Vector Load and Store Instructions LV v1, r1, r2 Vector Register v1 Memory Base, r1 Stride, r2 Vector Programming Model

  31. # Vector Code LI VLR, 64 LV V1, R1 LV V2, R2 ADDV.D V3, V1, V2 SV V3, R3 # C code for (i=0; i<64; i++) C[i] = A[i] + B[i]; # Scalar Code LI R4, 64 loop: L.D F0, 0(R1) L.D F2, 0(R2) ADD.D F4, F2, F0 S.D F4, 0(R3) DADDIU R1, 8 DADDIU R2, 8 DADDIU R3, 8 DSUBIU R4, 1 BNEZ R4, loop Vector Code Example

  32. Vector Instruction Set Advantages • Compact • one short instruction encodes N operations • Expressive, tells hardware that these N operations: • are independent • use the same functional unit • access disjoint registers • access registers in the same pattern as previous instructions • access a contiguous block of memory (unit-stride load/store) • access memory in a known pattern (strided load/store) • Scalable • can run same object code on more parallel pipelines or lanes

  33. Vector Arithmetic Execution V1 V2 V3 • Use deep pipeline (=> fast clock) to execute element operations • Simplifies control of deep pipeline because elements in vector are independent (=> no hazards!) Six stage multiply pipeline V3 <- v1 * v2

  34. Execution using one pipelined functional unit Execution using four pipelined functional units A[26] A[25] A[24] A[27] A[6] B[24] B[26] B[27] B[25] B[6] A[20] A[23] A[22] A[21] A[5] B[20] B[23] B[21] B[22] B[5] A[18] A[17] A[16] A[19] A[4] B[16] B[19] B[18] B[17] B[4] A[12] A[13] A[15] A[14] A[3] B[14] B[15] B[13] B[12] B[3] C[11] C[10] C[9] C[2] C[8] C[6] C[1] C[5] C[7] C[4] C[0] C[3] C[0] C[1] C[2] Vector Instruction Execution ADDV C,A,B

  35. Functional Unit Lane Vector Unit Structure Vector Registers Elements 0, 4, 8, … Elements 1, 5, 9, … Elements 2, 6, 10, … Elements 3, 7, 11, … Memory Subsystem

  36. Vector register elements striped over lanes [24] [25] [26] [27] [28] [29] [30] [31] [16] [17] [18] [19] [20] [21] [22] [23] [8] [9] [10] [11] [12] [13] [14] [15] [0] [1] [2] [3] [4] [5] [6] [7] T0 Vector Microprocessor (1995) Lane

  37. Vector Memory-Memory Code Example Source Code ADDV C, A, B SUBV D, A, B for (i=0; i<N; i++) { C[i] = A[i] + B[i]; D[i] = A[i] - B[i]; } Vector Register Code LV V1, A LV V2, B ADDV V3, V1, V2 SV V3, C SUBV V4, V1, V2 SV V4, D Vector Memory-Memory vs.Vector Register Machines • Vector memory-memory instructions hold all vector operands in main memory • The first vector machines, CDC Star-100 (‘73) and TI ASC (‘71), were memory-memory machines • Cray-1 (’76) was first vector register machine

  38. Vector Memory-Memory vs. Vector Register Machines • Vector memory-memory architectures (VMMA) require greater main memory bandwidth, why? • All operands must be read in and out of memory • VMMAs make if difficult to overlap execution of multiple vector operations, why? • Must check dependencies on memory addresses • VMMAs incur greater startup latency • Scalar code was faster on CDC Star-100 for vectors < 100 elements • For Cray-1, vector/scalar breakeven point was around 2 elements • Apart from CDC follow-ons (Cyber-205, ETA-10) all major vector machines since Cray-1 have had vector register architectures (we ignore vector memory-memory from now on)

  39. Vectorized Code Scalar Sequential Code load load load load Iter. 1 load load add Time add add store load store store load Iter. 1 Iter. 2 Vector Instruction Iter. 2 add store Automatic Code Vectorization for (i=0; i < N; i++) C[i] = A[i] + B[i]; Vectorization is a massive compile-time reordering of operation sequencing  requires extensive loop dependence analysis

  40. for (i=0; i<N; i++) C[i] = A[i]+B[i]; A B C Remainder 64 elements + + + Vector Stripmining ANDI R1, N, 63 # N mod 64 MTC1 VLR, R1 # Do remainder loop: LV V1, RA DSLL R2, R1, 3 # Multiply by 8 DADDU RA, RA, R2 # Bump pointer LV V2, RB DADDU RB, RB, R2 ADDV.D V3, V1, V2 SV V3, RC DADDU RC, RC, R2 DSUBU N, N, R1 # Subtract elements LI R1, 64 MTC1 VLR, R1 # Reset full length BGTZ N, loop # Any more to do? Problem: Vector registers have finite length Solution: Break loops into pieces that fit into vector registers, “Stripmining”

  41. Memory operations • Load/store operations move groups of data between registers and memory • Three types of addressing • Unit stride • Contiguous block of information in memory • Fastest: always possible to optimize this • Non-unit(constant) stride • Harder to optimize memory system for all possible strides • Prime number of data banks makes it easier to support different strides at full bandwidth • Indexed (gather-scatter) • Vector equivalent of register indirect • Good for sparse arrays of data • Increases number of programs that vectorize

  42. Vector Processor Unpipelined DRAM Unpipelined DRAM Unpipelined DRAM Unpipelined DRAM Unpipelined DRAM Unpipelined DRAM Unpipelined DRAM Unpipelined DRAM Addr Mod 8 = 7 Addr Mod 8 = 6 Addr Mod 8 = 0 Addr Mod 8 = 2 Addr Mod 8 = 3 Addr Mod 8 = 4 Addr Mod 8 = 5 Addr Mod 8 = 1 Interleaved Memory Layout • Great for unit stride: • Contiguous elements in different DRAMs • Startup time for vector operation is latency of single read • What about non-unit stride? • Above good for strides that are relatively prime to 8 • Bad for: 2, 4

  43. How to get full bandwidth for Unit Stride? • Memory system must sustain (# lanes x word) /clock • No. memory banks > memory latency to avoid stalls • m banks m words per memory latency l clocks • if m < l, then gap in memory pipeline: clock: 0 … l l+1 l+2 … l+m- 1 l+m … 2 l word: -- … 0 1 2 … m-1 -- … m • may have 1024 banks in SRAM • If desired throughput greater than one word per cycle • Either more banks (start multiple requests simultaneously) • Or wider DRAMS. Only good for unit stride or large data types • More banks/weird numbers of banks good to support more strides at full bandwidth

  44. Enhancing Vector Performance Five techniques for improving the performance of a vector processor. • Chaining • Conditionally Executed Statements • Scatter/Gather for Sparse Matrices • Multiple Lanes • Pipelined Instruction Start-Up

  45. V1 V2 V3 V4 V5 Chain Chain Load Unit Mult. Add Memory (1) Vector Chaining • Vector version of register bypassing • introduced with Cray-1 LV v1 MULV v3,v1,v2 ADDV v5, v3, v4

  46. Without chaining, must wait for last element of result to be written before starting dependent instruction Load Mul Time Add • With chaining, can start dependent instruction as soon as first result appears Load Mul Add Vector Chaining Advantage

  47. Implementations of Chaining • Early implementations worked like forwarding, but this restricted the timing of the source and destination instructions in the chain. • Recent implementations use flexible chaining, which requires simultaneous access to the same vector register by different vector instructions, which can be implemented either by adding more read and write ports or by organizing the vector-register file storage into interleaved banks in a similar way to the memory system.

  48. (2) Vector Conditional Execution Problem: Want to vectorize loops with conditional code: for (i=0; i<N; i++) if (A[i]>0) then A[i] = B[i]; Solution: Add vector mask (or flag) registers • vector version of predicate registers, 1 bit per element …and maskable vector instructions • vector operation becomes NOP at elements where mask bit is clear Code example: CVM ; Turn on all elements LV VA, RA ; Load entire A vector L.D F0,#0 ; Load FP zero into F0 SGTVS.D VA, F0 ; Set bits in mask register where A>0 LV VA, RB ; Load B vector into A under mask SV VA, RA ; Store A back to memory under mask

  49. Simple Implementation • execute all N operations, turn off result writeback according to mask Density-Time Implementation • scan mask vector and only execute elements with non-zero masks M[7]=1 M[7]=1 A[7] B[7] M[6]=0 M[6]=0 A[6] B[6] A[7] B[7] M[5]=1 M[5]=1 A[5] B[5] M[4]=1 M[4]=1 A[4] B[4] C[5] M[3]=0 M[3]=0 A[3] B[3] M[2]=0 C[4] M[1]=1 M[2]=0 C[2] M[0]=0 C[1] M[1]=1 C[1] Write data port M[0]=0 C[0] Write Enable Write data port Masked Vector Instructions

  50. A[7] M[7]=1 A[7] A[7] M[7]=1 A[5] M[6]=0 A[6] B[6] M[6]=0 A[4] M[5]=1 A[5] A[5] M[5]=1 A[1] M[4]=1 A[4] A[4] M[4]=1 M[3]=0 A[3] A[7] B[3] M[3]=0 M[2]=0 A[2] A[5] B[2] M[2]=0 M[1]=1 A[1] A[4] A[1] M[1]=1 M[0]=0 A[0] A[1] B[0] M[0]=0 Expand Compress Compress/Expand Operations • Compress packs non-masked elements from one vector register contiguously at start of destination vector register • population count of mask vector gives packed vector length • Expand performs inverse operation Used for density-time conditionals and also for general selection operations

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