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Microprocessor system architectures – IA32 paging. Jakub Yaghob. Control – global setting. Paging modes. Address translation – 4K pages , 32-bit physical address. Address translation – 4 M pages , 32-bit physical address. Page Directory – 4K/32b. Page Table – 4K/32b.

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Microprocessor system architectures ia32 paging

Microprocessor system architectures – IA32 paging

Jakub Yaghob


Control global setting
Control – global setting



Address translation 4k pages 32 bit physical address
Address translation – 4K pages, 32-bit physical address


Address translation 4 m pages 32 bit physical address
Address translation – 4Mpages, 32-bit physical address


Page directory 4k 32b
Page Directory – 4K/32b


Page table 4k 32b
Page Table – 4K/32b


Page directory 4m 32b
Page Directory – 4M/32b


Pae page address extension
PAE – Page Address Extension

  • Widens possibility of addressing physical memory to 36 bits (64GB)

  • Available from Pentium Pro

  • Paging data structures changed

    • Other release of OS (different compilation)

    • PDBR changed

  • Bit NX (No eXecute)/XD (eXecution Disabled)

    • NewerAMD/Pentium 4


Address translation 4k pages 3 6 bit physical address
Address translation – 4K pages, 36-bit physical address


Address translation 2m pages 3 6 bit physical address
Address translation – 2Mpages, 36-bit physical address


Page table entries 4k 36b
Page table entries – 4K/36b



Pse 36 page size extension 36 bit
PSE-36 – Page Size Extension 36-bit

  • An alternate method to the PAE

  • Allows addressing of 36 bits physical address space using 4M pages

  • Available fromPentium III

  • Only whenPSE-36 flag available (CPUID[17])


Address translation 4m pages 3 6 bit physical address
Address translation – 4Mpages, 36-bit physical address


Page directory 4m 36b
Page Directory – 4M/36b


Page fault
Page fault

  • All paging problems caught by #PF exception

    • Flag P set to 0

    • Access rights violation

  • Page table or page directory


Protection
Protection

  • U/S flag

    • =0 – supervisor mode

      • CPL 0-2

    • =1 – user mode

      • CPL 3

  • R/W flag

    • =0 – read-only

      • Not used insupervisor mode, until flagWP (CR0[16]) is set

    • =1 – read/write

  • NX/XD flag

    • =0 – can execute

    • =1 – no execute


Tlb translation lookaside buffer
TLB – Translation Lookaside Buffer

  • Associative memory for accelerating translation from linear to physical address

  • TLB purging

    • Explicitly usingmovcr3,eax

    • Implicitly during task change – reading new CR3

    • Entries with G flag set are not purged when PGE is set (CR4[7])

  • Selective entry purging

    • InstructionINVLPG


Pae in long mode
PAE in long mode

  • Max limits

    • 64-bit linear address

    • 52-bit physical address

  • Current implementation

    • 48-bit linear address

    • 40-bit physical address

  • Setting

    • PAE must be enabled before switching to long mode


Address translation 4k pages in long mode
Address translation – 4K pages in long mode


Address translation 2m pages in long mode
Address translation – 2Mpages in long mode


Page table entries 4k long mode i
Page table entries – 4K/long mode – I


Page table entries 4k long mode ii
Page table entries – 4K/long mode – II


Page table entries 2m long mode
Page table entries – 2M/long mode


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