Java Flowpaths: Efficiently Generating Circuits for Embedded Systems from Java

1. Java Flowpaths: Efficiently Generating Circuits for Embedded Systems from Java WorldComp ESA 2006 Las Vegas, Nevada EXCERPT Darrin Hanna, Michael DuChene, Girma Tewolde, Jay Sattler Oakland University, Rochester, Michigan Kettering University, Flint, Michigan June 27, 2006

2. Overview • Motivation • Background • Some examples • Class Instantiation in Flowpaths • Implementing Parallel Flowpaths • Results

3. Background • Flowpaths – a type of SPP Generated using a Particular Method for Translating Stack-based Programs Directly to FPGAs • Java  Java Byte Codes (Stack-based IR) • Forth • Words as Flowpaths: Ops, Connections, and State Machines • Converting Flowpaths to VHDL • Euclid’s Greatest Common Divisor Algorithm • Sieve of Eratosthenes: A performance comparison

4. Flowpaths – a type of SPP Generated using a Particular Method for Translating Stack-based Programs Directly to FPGAs Executing the algorithm as an SPP without a Microprocessor

5. Java Byte Codes as Flowpaths: Ops, Connections, and State Machines FRAME • Each thread has a JVM stack that stores frames • A frame is created each time a method is invoked Local Variable Array Constant Pool from Class invoking the method Operand Stack

6. Java Byte Codes as Flowpaths: Ops, Connections, and State Machines Flowpath Datapath Controller LOAD-EXECUTE-STORE STACK MANIPULATION OP OP OP MUX FRAME OP Local Variable Array Operand Stack Local Variables Operand Stack

7. Java Byte Codes as Flowpaths: Ops, Connections, and State Machines … iload_1 iload_2 iadd istore_1 … TRADITIONAL LOAD-EXECUTE-STORE STACK MANIPULATION 4 clock cycles • FLOWPATHS • Operations – Sequential • isub, iadd, etc… • Data Manipulation – Connections • iload, istore • ZERO clock cycles Only 1 clock cycle

8. Converting Flowpaths to VHDL Euclid’s GCD Algorithm:

9. Converting Flowpaths to VHDL Euclid’s GCD Algorithm: Methods that implements each variable as a register results in over-crowded routing

10. Converting Flowpaths to VHDL Euclid’s GCD Algorithm

11. Sieve of Eratosthenes

12. Sieve of Eratosthenes A circuit and state machine developed “by hand” observing the behavior of the algorithm Serves as an optimal implementation

13. Sieve of Eratosthenes Experiments using a Xilinx Spartan IIE FPGA FPGA-VHDL (hand implementation) took 233 Slices Flowpath took 295 Slices

14. Experimental Results Quick Sort algorithm sorting 4096 random numbers

15. Experimental Results Genetic Algorithm - population size of 50, probability of mutation 10%, and a probability of cross-over 20% run for 10 generations

16. Multi-threaded Experimental Results(Parallel) JStamp 121,200 clock cycles (Microcontroller that executes Java bytecode directly) ~20,000 gates The Producer/Consumer Test took 40 clock cycles in the Flowpath!

17. Conclusion • Hardware can be generated directly from Java programs using Flowpaths • There are enormous performance benefits to using Flowpaths instead of a JVM on a microprocessor • Parallel algorithms with or without shared resources can easily be developed. These will truly execute in parallel, in the hardware sense

18. Oakland University Rochester, Michigan June 27, 2006 Thank You! Darrin Hanna, Michael DuChene, Girma Tewolde, Jay Sattler