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ELEC 516 Digital VLSI System Design and Design Automation (Spring 2010) Tutorial on VHDL Language -- Introduction and Design Methodology. By Qian zhiliang (Toby) Reference ELEC 516 tutorials of previous semesters by Michael Ling & Hui shao

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slide1

ELEC 516 Digital VLSI System Design and Design Automation (Spring 2010)Tutorial on VHDL Language -- Introduction and Design Methodology

By Qian zhiliang (Toby)

Reference

ELEC 516 tutorials of previous semesters by Michael Ling & Hui shao

“VHDL : Analysis and modeling of digital systems” by Navabi, 2nd edition

vhdl background
VHDL Background
  • An integrated design environment is useful for better design efficiency in the large digital systems.
  • Ideal design environment:
    • High level description of the system which uniquely defines a hardware should be understandable.
    • Additional details enable simulation and testing is added to the initial description when design processes
    • The initial description evolves to a detailed description for the final generated hardware
  • Language is needed to describe hardware in various levels
  • Why VHDL :
  • includes facilities for describing logical structure and function of a system from system level down to gate level.
  • it’s intended as a modeling language for modeling & specification
  • Now, we can also use it for hardware synthesis
modeling digital systems
Modeling Digital Systems
  • Digital systems encompasses a range of system from low-level components to complete system-on-chip and broad level models
  • A systematic methodology of design : decompose & compose primitive components that performs required function
  • expressing system requirements in a complete and unambiguous way ( VHDL , SystemC, Verilog, SystemVerilog, C++ )
  • test a design to verify the function
  • Synthesizing an implementation in a target technology ( ASIC or FPGA)
vhdl features
VHDL Features
  • VHDL is usable for design documentation, high-level design, simulation, synthesis and testing of hardware, and as a driver for a physical design tool.
  • VHDL are concurrent language. It means that transfer statements, description of components, and instantiations of gates or logical unit are all executed simultaneously.
  • Hierarchical specification- essential for multi-level hardware language. A design consists of an interface description and a separate part for describing its operation.
    • The operation of a system or subsystems can be specified based on its functionality, or it can be specified structurally in terms of its smaller sub-components
other considerations
Other Considerations:
  • Library Support
    • VHDL support accessing different libraries
    • A library stores several specifications or primitives for a function
  • Sequential Statement
    • While concurrent components, some subsections may be software like sequentially controlled
    • VHDL has sequential statements, e.g. case, if-then-else, loop…
  • Generic Design
    • To configure the generic description of a component (same function) for different designs
    • configurable for size, timing, loading and operating conditions.
hdl software programming language c java
HDL & software programming language (C++ , Java)
  • Type declaration and usage
    • Besides bit and boolean types, VHDL support integer, floating-point, enumerate types and user defined types
    • Capability to redefine language operators
  • Ability to define and use of subprograms, e.g. functions and procedures
  • Timing Control
    • Schedule values to signals and delay the assignment of values until later time
    • Handshaking-ability to wait for occurrence of an event or for a specific time of duration
    • Constructs for clock edge detection, delay specification, setup and hold time specification, pulse width checking, and setting various time constraints should be provided
an vhdl environment example
An VHDL Environment Example

Analyzer : a syntax analyzer

Synthesizer : mapping a description to a specific or generic library

Simulator : according to the timing specification of the library , simulate the output based on the testbench

synthesis
Synthesis
  • From high level description to the gate level netlist, it is usually with the help of synthesis tools.
  • For VHDL, only a subset of the language is synthesizable, and different tools support different subsets.
  • RTL style code is encouraged because it is synthesizable.
  • In RTL, it is possible to split the code into two blocks (e.g. process) that contain either purely combinational logic or registers.
  • FSM is also synthesizable

For simulation, we can use the unsynthesizable VHDL or Verilog code in the test bench to generate the stimulus.

design methodology based on vhdl
Design Methodology Based on VHDL
  • Top-Down Design and bottom-up implementation
  • Simulations/Validations
simulation validations
Simulation/Validations
  • Testbench—Verify the specified functionality of a design.
    • Provide the stimulus for the Device Under Test (DUT).
    • Analyze the DUT\'s responses or stores them in a file.
vhdl basic concept
VHDL Basic Concept
  • A given circuit is presented as a Design Entity
  • A design entity consists of two descriptions: an interface description and one or more architectural bodies
  • Entitydeclaration:

ENTITY component nameIS

input and output ports

physical and other parameters

END component name;

ARCHITECTURE identifier OF

component nameIS

declarations.

BEGIN

specification of the functionality of

the component in terms of its input

lines and as influenced by physical

and other parameters

END identifier;

  • Architecture declaration:
vhdl basics
VHDL Basics :
  • Architectural bodies describes the function of a component which depends on input-output signals and other interface-specified parameters
  • Several architectural specifications with different identifiers can exist for one component with a given interface description

Entity component_i IS PORT(..)

ARCHITECTURE

behavioral

OF

component_i

IS

...

ARCHITECTURE

dataflow

OF

component_i

IS

...

ARCHITECTURE

structural

OF

component_i

IS

...

other

ARCHITECTURES

OF

component_i

IS

...

vhdl example
VHDL Example:
  • Comments : -- comments or …comments…
  • Identifiers : very similar to programming language, has reserve word like “abs” “after” etc which we can’t use to name an entity or architecture
  • Numbers : 46E09 , 34.0e-08 (integers and real literals are valid form)
  • Bit Strings : B for binary, O for octal (based 8), X for hexadecimal (base 16)
example count the number of 1 s in the input vector of length 3
Example: Count the Number of 1’s in the Input Vector of Length 3

Architecture behavioral of ONES_CNT is

begin

process(A)

variable NUM: INTEGER range 0 to 3;

begin

NUM :=0;

for I in 0 to 2 loop

if A(I) = ‘1’ then

NUM := NUM +1;

end if;

end loop;

Interface description

entity ONES_CNT is

port(A: in std_logic_vector(2 downto 0);

C:out std_logic_vector(1 downto 0));

--- Truth Table

--- A2 A1 A0 C1 C0

--- 0 0 0 0 0

--- 0 0 1 0 1

--- 0 1 0 0 1

--- 0 1 1 1 0

--- 1 0 0 0 1

--- 1 0 1 1 0

--- 1 1 0 1 0

--- 1 1 1 1 1

end ONES_CNT;

case NUM is

when 0 => C <= “00”;

when 1 => C <= “01”;

when 2 => C <= “10”;

when 3 => C <= “11”;

end case;

end process;

end behavioral;

data flow model of the 1 s counter another implementation
Data Flow Model of the 1’s Counter – another implementation
  • C1 = (A1)(A0) + (A2)(A0) + (A2)(A1)
  • C0 = (A2)(A1)(A0) + (A2)(A1)(A0) + (A2)(A1)(A0) + (A2)(A1)(A0)

architecture DATA_FLOW of ONES_CNT is

begin

C(1) <= (A(1) and A(0)) or (A(2) and A(0)) or (A(2) and A(1));

C(0) <= (A(2) and not A(1) and not A(0)) or (not A(2) and not A(1) and A(0)) or (A(2) and A(1) and A(0)) or (not A(2) and A(1) and not A(0));

end DATA_FLOW;

hierarchical implementation of 1 s counter
Hierarchical Implementation of 1’s Counter
  • Hierarchical Design is more preferable in large system design :

ONE_CNT

Architecture structural of ONES_CNT is

begin

C(1) <= MAJ3(A);

C(0) <= OPAR3(A);

end structural;

MAJ3

OPAR3

Entity AND2 is

port (I1,I2: in std_logic; O: out std_logic);

end AND2;

architecture BEHAVIOR1 of AND2 is

begin

O <= I1 and I2;

end BEHAVIOR1;

AND2

OR3

AND3

OR4

Entity OR3 is

port (I1,I2,I3: in std_logic; O: out std_logic);

end OR3;

architecture BEHAVIOR2 of OR3 is

begin

O <= I1 or I2 or I3;

end BEHAVIOR2;

structure description of maj3 gate
Structure Description of MAJ3 Gate

Entity MAJ3 is

port(X:in std_logic_vector(2 downto 0); Z:out std_logic);

end MAJ3;

architecture AND3_OR of MAJ3 is

component AND2C

port (I1,I2: in std_logic; O: out std_logic);

end component;

component OR3C

port (I1,I2,I3 in std_logic; O: out std_logic);

end component;

for all: AND2C use entity AND2(BEHAVIOR1);

for all: OR3C use entity OR3(BEHAVIOR2);

signal A1, A2, A3:std_logic;

begin

G1: AND2C

port map (X(0),X(1),A1);

G2: AND2C

port map (X(0),X(2),A2);

G3: AND2C

port map (X(1),X(1),A3);

G4: OR3C

port map (A1,A2,A3,Z);

end AND3_OR;

A1

X(1)

Z

X(0)

A2

X(2)

X(1)

A3

X(2)

model testing
Model Testing
  • Test bench - top level entity to test the other entity.
  • The test bench must contain the circuit under test and should have sources for providing data to its input

Entity TEST_BENCH

is end TEST_BENCH;

use WORK. all;

architecture ONES_CNT1 of TEST_BENCH is

signal A: std_logic_vector(2 downto

0);

signal C: std_logic_vector(1

downto 0);

component ONES_CNTA

port(A: in std_logic_vector(2

downto 0);

C: out std_logic_vector(1

downto 0));

end component;

for L1: ONES_CNTA use entity

ONES_CNT(behavioral)

begin

L1: ONES_CNTA

port map(A,C);

process

begin

A<= “000” after 1 ns,

“001” after 1 ns,

“010” after 1 ns,

“011” after 1 ns,

“100” after 1 ns,

“101” after 1 ns,

“110” after 1 ns,

“111” after 1 ns;

wait;

end process;

end ONES_CNT1;

slide19

ELEC 516 Digital VLSI System Design and Design Automation (Spring 2010)Tutorial on VHDL Language -- VHDL language syntax

By Qian zhiliang (Toby)

Reference

ELEC 516 tutorials of previous semesters by Michael Ling & Hui shao

“VHDL : Analysis and modeling of digital systems” by Navabi, 2nd edition

entity
Entity
  • The entity specifies the design entity name and the input/output interface.
  • Port Type:
    • in
    • out
    • buffer
    • inout

entity HALFADDER is   port(      A, B:   in   std_logic;      SUM, CARRY: out std_logic);end HALFADDER;

entity ADDER is    port(      A, B:    in     integer range 0 to 3;      SUM:   out integer range 0 to 3;      CARRY: out std_logic );end ADDER;

architecture
Architecture
  • The architecture contains the implementation for an entity which may be either a behavioral description (behavioral level or, if synthesizable, RT level) or a structural netlist or a mixture of those alternatives.
    • Declaration part (datatype, constants, signals, components,…)
    • Definition part (signal assignment, process, concurrent statements, components initializations,…)

architecture RTL of HALFADDER isbegin   SUM      <= A xor B;   CARRY <= A and B;end RTL;

hierarchical model and components initialization
Hierarchical Model and Components Initialization
  • architecture STRUCT of FULLADDER iscomponent HALFADDER    port (A, B :                in   std_logic;            SUM, CARRY : out std_logic);  end component;  component ORGATE    port (A, B : in   std_logic;            RES : out std_logic);  end component;  signal W_SUM, W_CARRY1, W_CARRY2: std_logic;begin  MODULE1: HALFADDER     port map( A, B, W_SUM, W_CARRY1 );     MODULE2: HALFADDER     port map ( W_SUM, CARRY_IN,                      SUM, W_CARRY2 );     MODULE3: ORGATE     port map ( W_CARRY2, W_CARRY1, CARRY ); end STRUCT;

An alternative component initialization:

MODULE1: HALFADDER                     port map (  A     => A,                                     SUM     => W_SUM,                                      B           => B,                                     CARRY => W_CARRY1 );   . . .

configuration
Configuration
  • Selects architecture for top-level entity
  • Selects entity/architecture pairs for instantiated components
  • Generates the hierarchy
  • Creates a simulation object
  • Default binding rules:
    • selects entity with same name as component
    • signals are associated by name
    • last compiled architecture is used
an example for configuration of fulladder
An example for configuration of fulladder
  • configuration CFG_FULLADDER of FULLADDER is   for STRUCT       for MODULE2: HALFADDER          use entity work.HALFADDER(GATE);          port map ( U => A,                          V => B,                          X => SUM,                          Y => CARRY );       end for;       for others : HALFADDER          use entity work.HALFADDER(RTL);       end for;  end for;end CFG_FULLADDER;

Binding different architecture model of half adder

vhdl operator
VHDL Operator
  • Logical operators: e.g. not, and, or, nand, nor, xor
    • for operands of the predefined BIT and BOOLEAN types.
  • Relational operators: =, /=, <, <=, > , >=
  • Shift operations: SLL, SLA, SRL, SRA. ROL, ROR
  • arithmetic operators: +, -, *, /, **, ABS
    • operators must be of the same type and the result affects the types of operand.
  • The concatenation operator: &
    • used of concatenating arrays of elements. The types of the elements in concatenated arrays must be the same. This operator is particularly useful for merging buses or registers.
    • E.g. x_byte & y_byte => concatenate 2 8-bit array to 1 16-bit array; a&b<=“10”…
object type
Object Type
  • Signal
    • It represents interconnection wires that connect component instantiation ports together.
    • It has a time component associated with them. The assignment symbols for signals is <= which has a nonzero time component.
  • Variable
    • It is used for local storage of temporary data, visible only inside a sequential bodies of VHDL, and they are local to the bodies. Value assignment :=
    • Sequential bodies include processes, functions and procedures
  • Signal assignments are delayed assignments, while variable assignments are instantaneous assignments.
  • Constant
    • It names specific values.
signals and variables
Signals and Variables

Case I:

0t 2t 4t 6t 8t

X 1 4 5 5 3

Y 2 2 2 3 2

AS 2 2 8 10 15

Z 0 3 2 2 2

BS 2 2 5 10 12

Case I: AS<=X*Y after 2 ns;

BS <=AS + Z after 2 ns;

Case II: AV:=X*Y;

BV :=AV + Z;

1

4

5

5

3

X

2

2

2

3

2

Y

Case II:

0t 2t 4t 6t 8t

X 1 4 5 5 3

Y 2 2 2 3 2

AV 2 8 10 15 6

Z 0 3 2 2 2

BV 2 11 12 17 8

0

3

2

2

2

Z

t1

t1+2

t1+4

t1+6

data type
Data Type
  • Predefined types: Integer, Real, Boolean, Bit, Severity_level, and Character..
  • logic - three-level logic (0,1,Z) for describing logic level at lowest level of abstraction.Ex,std_logic defined by IEEE library
  • floating point - specify the requirements for a floating point processor in terms of transformations on real numbers.
  • Every object and expression has a single, uniquely determinable type and those types cannot be mixed in expressions or in assignments of values to objects
  • Scalar type - a type whose values cannot be decomposed into more atomic values. It includes integer types, floating point types, enumeration types and physical types
data type cont
Data Type (cont.)
  • Example of scalar type:
    • type Byte is range -128 to 127;
    • type Bit_position is range 7 downto 0;
    • type Decimal_int is range -1E9 to 1E9;
  • Enumeration types have as their values enumeration literals. An enumeration literal is either an identifier or a character literal. E.g. type three_level_logic is (‘0’,’1’,’Z’);
  • Physical types specifies a range constraint, one base unit, and zero or more secondary units, each secondary unit being an integral multiple of the base unit e.g.

type Resistance is range 1 to 10E9

units

ohm; -- the base unit

kohm = 1000 ohm; -- secondary unit, multiple of base unit

end units;

  • Other data types issues: composite types, subtypes, attributes and predefined operators for a type
predefined attributes
Predefined Attributes
  • Array attribute, e.g. ‘left, ‘right, ‘high, ‘low…

e.g.. A \'left is left bound of index range of A

  • Type attribute, e.g. ‘right, ‘left, ‘high, ‘low, ‘leftof…

e.g.. A’ right is the right bound of index range of A

  • Signal attribute, e.g.
    • ‘stable
    • ‘event :True if there is an event on identifier in the current simulation cycle
    • ‘last_event :The time interval since last event on the identifier
    • ‘last_value : The value of the identifier just before the last event
    • ‘active

These attributes are often used in checking the timing behavior within a model

concurrent and sequential statement
Concurrent and Sequential Statement
  • Concurrent Statement
    • Executed at the same time, independent of the order in which they appear
  • Sequential Statement
    • Executed according to the order in which they appear
    • Permitted only within processes, functions and procedures
    • Used to describe algorithms
concurrent statement
Concurrent Statement

architecture EXAMPLE of CONDITIONAL_ASSIGNMENT isbegin   -- Concurrent version of conditional signal assignment Z_CONC <= B when X = "1111" else                         C when X > "1000" else                         A;

  • Conditional Signal Assignment

TARGET<= VALUE_1 when

CONDITION_1 else

VALUE_N

  • Selected Signal Assignment

With EXPRESSION select

TARGET<=VALUE_1 when CHOICE_1,

VALUE_2 when CHOICE_2|CHOICE_3,

VALUE_3 when CHOICE_4 to CHOICE_5,

VALUE_N when others

architecture EXAMPLE of SELECTED_ASSIGNMENT isbegin   -- Concurrent version of selected signal assignmentwith X select      Z_CONC <= A when 0,                           B when 7 | 9,                           C when 1 to 5,                           0 when others;

sequential statement
Sequential Statement

 process (A, B, C, X)   begin if  (X = "1111")  then         Z <= B; elsif  (X > "1000")  then         Z <= C; else         Z <= A; end if;   end process;

  • If statement
  • Case statement
  • For loop statement

  process (A, B, C, X)   begin case  X  is when  0  =>            Z <= A; when  7  |  9  =>            Z <= B; when  1 to 5  =>            Z <= C;  when others =>            Z <= 0; end case;           end process;

  process (A)   begin      Z <= "0000"; for  I  in  0 to 3  loop         if (A = I) then            Z(I) <= `1`;         end if; end loop;   end process;

sequential statement cont
Sequential Statement (cont.)
  • Wait Statement
    • The wait statement is a highly behavioral construct for modeling delays, handshaking, and hardware dependencies. This statement can be used only in procedures and processes that do not have the optional sensitivity list.
    • When a program flow reaches a wait statement, the process or procedure that encloses it is suspended. The sequential body resumes after the conditions specified by the wait statement are met.
      • wait for SPECIFIC_TIME; e.g. wait for 10ns
      • wait on SIGNAL_LIST; e.g. wait on clk --this wait until an event happens on clk
      • wait until CONDITION; e.g. wait until clk=‘1’
      • wait;
process
Process
  • Contains sequentially executed statements
  • Exists within an architecture only
  • Several processes run concurrently
  • Execution is controlled either via
    • sensitivity list (contains trigger signals), or
    • wait-statements
  • The process label is optional

Sensitivity list

architecture RTL of AND_OR_XOR isbeginA_O_X:  process  (A, B)                        begin      Z_OR   <= A or    B;      Z_AND <= A and B;      Z_XOR <= A xor  B;     end process  A_O_X ;end RTL;

architecture RTL of AND_OR_XOR isbeginA_O_X:  process                        begin      Z_OR   <= A or    B;      Z_AND <= A and B;      Z_XOR <= A xor  B; wait on A,B;

     end process  A_O_X ;end RTL;

clocked process clock edge detection
Clocked Process: Clock Edge Detection

If

clock_signal_ name\'EVENT and clock_signal_name=\'1\'

[clock_signal_ name=\'1\' and clock_signal_ name\'EVENT

not clock_signal_ name\'STABLE and clock_signal_ name=\'1\'

clock_signal_ name=\'1\' and not clock_signal_ name\'STABLE

RISING_EDGE ( clock_signal_ name) ];

Logic Statements;

end if;

wait until

clock_signal_ name\'EVENT and clock_signal_ name=\'1\'

[clock_signal_ name=\'1\' and clock_signal_ name\'EVENT

not clock_signal_ name\'STABLE and clock_signal_ name=\'1\'

clock_signal_ name=\'1\' and not clock_signal_ name\'STABLE

RISING_EDGE ( clock_signal_ name) ];

Logic Statements;

event and transaction in vhdl
Event and Transaction in VHDL
  • Event is a kind of assignment which changes the previous data value
  • Transaction is true just when an assignment occurs, even this assignment doesn’t change the data value

Q & A on VHDL ?

think about synthesis
Think about Synthesis
  • VHDL coding is a little different from the other programming languages. It is concurrent operation and is closely related to the hardware implementation.
  • Think about the synthesis when programming.
    • Different coding styles results different hardware architecture

process (SEL,A,B) variable  TMP : std_logic;begin   if SEL = `1` then TMP  := B;   else TMP  := C;   end if;   Z <= A + TMP;end process;

process (SEL,A,B)begin   if SEL = `1` then      Z <= A + B;   else      Z <= A + C;   end if;

end process;

think about synthesis cont
Think about Synthesis (cont.)
  • Some times coding may be not synthesizable
    • Write RTL or FSM description for your design
other issues about vhdl

R

target1

C

Other Issues about VHDL
  • Inertial Delay and Transport Delay (Signal Assignment)
    • Signal assignment can have inertial delay and transport delay
      • Inertial delay can be used to model capacitive networks or gates. If the input pulse less than the inertial delay, it would be rejected. It’s the default option for the delay
      • Delays through transmission lines and networks with virtually infinite frequency response can be modeled by transport delay. Regardless the input pulse width, the input can be totally transmitted by the networks or gates
other issues cont
Other issues ( cont.)

We can filter the small-length pulse dedicatedly

other issues on vhdl
Other issues on VHDL :
  • Delta Delay
    • In VHDL, time delay can be specified in two ways,e.g.

(1) Y <= X -- delta delay

(2) Y<=X after 10 ns -- standard time unit delay

  • Delta delay is a period of time greater than 0 but less than any standard time unit.
slide43

ELEC 516 Digital VLSI System Design and Design Automation (Spring 2010)Tutorial on VHDL Language -- Modeling Example

By Qian zhiliang (Toby)

Reference

ELEC 516 tutorials of previous semesters by Michael Ling & Hui shao

“VHDL : Analysis and modeling of digital systems” by Navabi, 2nd edition

some example on models of digital logic primitives
Some Example on Models of Digital Logic Primitives
  • Combinational Primitives
      • gates
      • buffers
      • adders
      • multiplexers
      • decoders
      • encoders
      • comparators
      • shifters
      • ALU
  • Sequential Primitives
      • Flip-flops
      • Registers
      • Latches
      • Clock generator
combinational logic
Combinational Logic
  • GENERIC: provide a means for an instantiating (parent) component to pass values to an instantiated (child) component.
  • Typical uses: parameterize
    • timing,
    • the range of subtypes,
    • the number of instantiated subcomponents, and
    • the size of array objects
    • or simply to document physical characteristics such as temperature.
  • Default declaration

entity AND2 is

generic (DEL: TIME:=3ns)

port(I1,I2:in std_logic; O: out std_logic);

end AND2;

architecture DF of AND2 is

begin

O<= I1 and I2 after DEL;

end DF;

combinational logic cond
Combinational logic (cond.)
  • Specification of a generic parameter should beinside a component declaration and inside a component instantiation. e.g.

entity TEST is

port(a,b,c,d:IN STD_LOGIC; O:OUT STD_LOGIC);

end;

architecture A of TEST is

component n1 generic (DEL:TIME:=5);

port(I1,I2:in STD_LOGIC; O: out STD_LOGIC);

FOR ALL: n1 USE ENTITY WORK.AND2(DF);

SIGNAL: im1, im2 :STD_LOGIC;

BEGIN

g0: n1 PORT map (a,b,im1);

g1: n1 generic map(8) PORT map (c,d,im2);

g2: n1 generic map(10) PORT map (im1,im2,O);

end A;

1 bit adder 4 bit adder
1-bit Adder & 4-bit adder

entity FULL_ADDER is

generic(SUM_DEL, CARRY_DEL:TIME);

port(A,B,CI:in STD_LOGIC; SUM, CARRY:out STD_LOGIC);

end FULL_ADDER;

architecture DF of FULL_ADDER is

begin

SUM<= A xor B xor CI after SUM_DEL;

COUT <= (A and B) or (A and CI) or (B and

CI) after CARRY_DEL;

end DF;

entity 4_bit_Adder is

port(A,B:in std_logic_vector(3 down to 0); Cin:in std_logic;

S: out std_logic_vector(3 downto 0); Cout:out std_logic);

end 4_bit_Adder;

architecture A of 4_bit_Adder is

component n1: port(A,B,C1:in std_logic; Sum, Co: out std_logic);

End component;

FOR ALL: n1 USE ENTITY

WORK.FULL_ADDER(DF);

SIGNAL: im1, im2,im3:std_logic;

BEGIN

g0: n1 generic(3,4) PORT map

(A(0),B(0),Cin,S(0),im1);

g1: n1 generic(3,4) PORT map

(A(1),B(1),im1,S(1),im2);

g2: n1 generic(3,4) PORT map

(A(2),B(2),im2,S(2),im3);

g3: n1 generic(3,4) PORT map

(A(3),B(3),im3,S(3),Cout);

end A

shifter
Shifter

entity SHIFTER is

generic(del:time);

port(D_IN:in std_logic_vector(3 downto 0); SR,SL: in std_logic;IL,IR: in std_logic; D_OUT:out std_logic_vector(3 downto 0));

end SHIFTER;

architecture ALG of SHIFTER is

begin

process(SR,SL,D_IN, IL,IR)

variable CON: std_logic_vector(1 downto 0);

begin

CON := SR&SL;

case CON is

when “00” => D_OUT<= D_IN after DEL;

when “01” => D_OUT<= D_IN(2 downto 0) & IL after del;

when “10” => D_OUT<= IR & D_IN(3 downto 1) after del;

when “11” => D_OUT<= D_IN after DEL;

end case;

end process;

end ALG;

slide49
ALU

entity ALU is

generic(DEL:TIME);

port(A,B:in std_logic_vector(3 downto 0); CI: in std_logic_vector;

FSEL:in std_logic_vector(1 downto 0); F:out std_logic_vector(3 downto 0); COUT:out std_logic);

end ALU;

architecture ALG of ALU is

begin

process(A,B,CI,FSEL)

variable FV:std_logic_vector(3 downto 0); variable COUTV:std_logic;

begin

case FSEL is

when “00” => F<= A after DEL;

when “01” => F<= not(A) after DEL;

when “10” => ADD(A,B,CI,FV,COUTV);F <= FV after DEL;

when “11” => F<= A and B after DEL;

end case;

end process;

end ALG;

register model
Register Model

entity REG is

generic(DEL:time);

port(reset, load,clk:in std_logic; d_in:in std_logic_vector(3 downto 0); Q: inout std_logic_vector(3 downto 0));

end REG;

architecture DF of REG is

begin

REG: block(not clk’stable and clk=‘1’)

begin

Q <= guarded “0000” after DEL when RESET = ‘1’ else d_in after DEL when load = ‘1’ else

Q;

end block REG;

end DF;

guarded signal statement
Guarded Signal Statement
  • Block Statement: Guarded signal assignment executes only when the Boolean signal GUARD is TRUE. When GUARD is FALSE, the assignment does not execute even if events occur on the right hand side waveforms.
  • The GUARD signal can either be explicitly defined, or it can be provided implicitly by the use of a block statement with a guard expression.
  • A block statement is a concurrent statement. It can be used for three major purposes:
    • disable signal drivers by using guards
    • limit scope of declarations, including signal declarations
    • represent a portion of a design.
guarded signal statement cont
Guarded Signal Statement (cont.)
  • Sematic

block-label: block [(guard-expression)] [is]

[block-declarations]

begin

concurrent statements;

end block [block-label]

  • The block statement is very useful in modeling hardware elements that trigger on certain events, for example, flip-flops and clocked logic.
  • The statement part of the block statement can contain other concurrent statements. When nesting these statements, the implied GUARD signal within an inner block statement is defined by the guard expression of this statement only, and guard expressions do not automatically accumulate. For a GUARD signal to contain conditions of all its enclosing block statements, explicit ANDing of these expression must be done.
example of a flip flop
Example of a flip-flop

Entity de_flipflop is

generic (delay1: time:=4 ns;delay2:time :=5ns);

port(d,e,c: in std_logic;q, qb: out std_logic);

end de_flipflop;

Architecture guarding of de_flipflop is

begin

edge: block(c=‘1’and not c’stable)

begin

gate:block(e = ‘1’ and guard)

begin

q<= guarded d after delay1;

qb <= guarded not d after delay2;

end block gate;

end block edge;

end guarding;

q

d

e

c

shift register
Shift Register

entity SHIFTREG is

generic(latch_del:TIME);

port(clk,load,SR,SL,IL,IR:in std_logic; D:in std_logic_vector(3 downto 0); Q:inout std_logic_vector(3 downto 0));

end SHIFTREG;

architecture DF of SHIFTREG is

begin

SH: block(not clk’stable and clk=‘1’)

begin

Q <= guarded D after DEL when LOAD = ‘1’ else

Q(2 downto 0) &IL after DEL when SL = ‘1’ and SR = ‘0’ else

IR & Q(3 downto 1) after DEL when SL = ‘0’ and SR = ‘1’ else Q;

end block SH;

end DF;

clock generator oscillator
Clock Generator (Oscillator)

entity CLOCK_GENERATOR is

generic(per:time);

port(run:in std_logic; clk: out std_logic);

end CLOCK_GENERATOR;

architecture ALG of CLOCK_GENERATOR is

signal clock:std_logic;

begin

process(run,clock)

variable clke: std_logic :=0;

begin

if run =‘1’ and not run’stable then

clke :=‘1’;

clock <= transport ‘0’ after per/2;

clock <= transport ‘1’ after per;

end if;

if run =‘0’ and not run’stable then

clke := ‘0’;

end if;

if clock =‘1’ and not clock’stable

and clke = ‘1’ then

clock <= transport ‘0’ after per/2;

clock <= transport ‘1’ after per;

end if

clk <= clock;

end process;

end ALG

another clock generator using wait
Another Clock generator (using wait)

entity COSC is

generic(hi_time, lo_time:time);

port(run:in std_logic; clock: out std_logic := ‘0’);

end COSC;

architecture ALG of COSC is

begin

process

begin

wait until run = ‘1’;

while run =‘1’ loop

clock <=’1’;

wait for hi_time;

clock <=’0’;

wait for lo_time;

end loop

end process;

end ALG;

slide57

ELEC 516 Digital VLSI System Design and Design Automation (Spring 2010)Tutorial on Verilog Language --Brief overview

By Qian zhiliang (Toby)

Reference

Professor Don Thomas (Carnegie Mellon University ) ‘s slides

vhdl vs verilog
VHDL Vs. Verilog

Comparison of modeling capability between Verilog and VHDL

verilog usage
Verilog usage

Structure level description

Interface :

Port declaration

verilog usage1
Verilog usage

Data flow style description

Behavior style description

verilog features
Verilog features
  • Four Data value:

‘0’ , ‘1’ , ‘x’, ‘z’

  • Data representation Type
    • Binary 6’b100101
    • Hex 6’h25
  • Nets: physical connection between hardware elements

wire/tri

wand/triand

wor/trior

Supply0,supply1,tri0,tri1,trireg

  • Registers: Store value even if disconnected
verilog features1
Verilog features
  • Behavior description are introduced by initial and always statesment
  • Initial:

Initial

begin

……

end

  • always:

Always @ (sensitivity list)

begin

….

end

  • Points :
  • Initial statement execute once and then stop
  • Always statement continually loop
  • Initial statement is not used in the synthesis
  • Always statement is used in the synthesis

Behavioral statements can be used in both “initial” and “always” statements

e.g. If – then-else

case

for and while loop

verilog features2
Verilog features
  • Delay model & Event-driven simulation

Events are stored in a 2-D list ordered by the time

Events execute at a time and possibly schedule their output to change at a later time (a new event)

When no more events for the current time, move to the next

Events within a time are executed in arbitrary order

  • Timing model:

Gate level timing model – how time is advanced , what triggers new processing in the model. Whenever any inputs of the gate change, the output will be re-evaluated

Behavioral timing model : e.g. always @ (negedge clock) q=#10 data;

verilog features3
Verilog features
  • Test Bench

module main;

reg a, b, c;

wire sum, carry;

fulladder add(a,b,c,sum,carry);

initial

begin

a = 0; b = 0; c = 0;

#5

a = 0; b = 1; c = 0;

#5

a = 1; b = 0; c = 1;

#5

a = 1; b = 1; c = 1;

#5

end

endmodule

slide65

ELEC 516 Digital VLSI System Design and Design Automation (Spring 2010)Tutorial on Design flow--Brief overview

By Qian zhiliang (Toby)

Reference

EDA Group of NTU

slide66

Points :

  • VHDL / Verilog as design input
  • before synthesize, a behavioral simulation is needed to verify the functionality
  • after synthesize, a post-synthesize , pre-layout simulation is needed to verify the timing requirement
  • After place & route, the layout need to be extracted to carry out post layout simulation to ensure the timing requirement of the final layout
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