Tracking Millions of Flows In High Speed Networks for Application Identification

1. Tracking Millions of Flows In High Speed Networks for Application Identification Tian Pan, XiaoyuGuo, ChenhuiZhang, JunchenJiang, Hao Wu and Bin LiutTsinghua National Laboratory for Information Science and Technology Department of Computer Science and Technology, Tsinghua University, Beijing 10084, China 2012 Proceedings IEEE INFOCOM 通訊所 周啓松

2. Outline • Framework of system • External flow table management • ALFE replacement policy • Theoretical analysis • Evaluation • Conclusion

3. Framework of system

4. Emerge issues • On-chip SRAM is fast but insufficient to accommodate millions of concurrent flows which has to be stored in DDR or RLDRAM. • High hash collision rate and high cache miss rate. • It is hard to attach parallel off-chip DRAMs to gain performance improvement.

5. Purpose • An on-chip/off-chip hierarchical flow table to achieve high speed packet lookup and maintain tens of millions of flows. • Adaptive Least Frequently Evicted(ALFE), which keeps the elephant flows longer in the cache thus increasing the cache hit rate. • An efficient management scheme is proposed to exploit DRAM's burst feature. • Real trace evaluation on Altera FPGA platform indicates, with 200MHzinternal clock, small sized cache with 16K entries can achieve up to 80% hit rate, enabling more than 70Mpps line rate flow tracking even at the 40-byte packets.

6. Framework of the Proposed Application Identification

7. Design Trade-offs and System-level Optimization • Stateless TCP Handling without Flow Reconstruction • 3-Way shaking • FIN/RST • Fixed-allocated Hash Buckets to Exploit DRAM Bursts • Lower utilization of memory space • Cache Replacement Policy to Track Elephant Flows • Heavy-tailed distribution • lmpactof Misidentification

8. EXTERNAL FLOW TABLE MANAGEMENT

9. Flow Record Data Structure

10. Fixed-allocated Hash Bucket • How to store the flow records • How to read/write the memory efficiently

11. Device Independent Layer

12. Memory Swapping Logic

13. ALFE REPLACEMENT POLICY

14. Heavy-tailedness

15. Replacement Policy

16. THEORETICAL ANALYSIS

17. Poisson Queuing Network System

18. Throughput and Queue Length • The arrival rate of packets is less than the service rate: • The overall maximum throughput is determined by the maximum arrival rate which could be afforded by each part. • According to queuing theory, the system queue length is:

19. EVALUATION

20. Experiment Setup

21. On-chip Flow Cache

22. Off-chip Flow Table • The collision rate will be bounded less than when active flow number (AFN) is 4M.

23. Bucket Overflow NE BAW

24. Memory Utilization

25. Delay and Throughput • The 400MHz DRAM I/O interface transfers two data words per DRAM clock cycle. • The read latency is 6 DCs. • The write latency is 7 DCs. • The maximum throughput of DRAM is 44.44Mpps.

26. Trade-off between Utilization and Speed • When BAW is set to be 15 bits, the system reach optimal balance. • In this paper, the BAW is expanded to 21 bits to provide higher speed. • NE = 8 • Total entry number = 16.8M

27. Power

28. System Overall Performance • System Throughput • Overall throughput under different cache entry number

29. avalanche effect

30. Conclusion • Detail of Matching Engine should be listed. • Setup time of flow table should be taken into account System Overall Performance.