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CPRE 583 Reconfigurable Computing Lecture 4: 9/02/2011 (VHDL Overview 2 )

CPRE 583 Reconfigurable Computing Lecture 4: 9/02/2011 (VHDL Overview 2 ). Instructor: Dr. Phillip Jones (phjones@iastate.edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA. http://class.ece.iastate.edu/cpre583/. VHDL questions. Questions From Last Lecture?.

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CPRE 583 Reconfigurable Computing Lecture 4: 9/02/2011 (VHDL Overview 2 )

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  1. CPRE 583Reconfigurable Computing Lecture 4: 9/02/2011(VHDL Overview 2 ) Instructor: Dr. Phillip Jones (phjones@iastate.edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http://class.ece.iastate.edu/cpre583/

  2. VHDL questions Questions From Last Lecture?

  3. VHDL questions Questions From Last Lecture?

  4. HW1 due next Friday MP1 will be released Friday night. Common tools issue: You may need to set the path to vsim in ise If you are new to VHDL or need a refresher, then READ the Shock and Awe VHDL tutorial. Feel free to ask me questions if you need any further clarification on any topics Announcements/Reminders

  5. Detailed in class VHDL example An intro to MP1 A demo for getting started with MP1 Overview

  6. A better understanding of how to describe hardware structures using VHDL What you should learn

  7. VHDL: IF and CASE constructs • IF THEN ELSE can be mapped to a 2:1 Multiplexer (Mux) sel = b“0” IF (sel = ‘0’) THEN out_1 <= in_0; ELSE out_1 <= in_1 END IF; 2:1 Mux 4 x”C” in_0 4 x”C” out_1 4 x”D” in_1

  8. VHDL: IF and CASE constructs • Mapping a CASE statement to a 4:1 Mux CASE sel is WHEN “00” => out_1 <= in_0; WHEN “01” => out_1 <= in_1; WHEN “10” => out_1 <= in_2; WHEN “11” => out_1 <= in_3 WHEN OTHERS => out_1 <= in_0; END CASE; sel = b“10” 2 4 x”C” in_0 4:1 Mux 4 x”D” in_1 4 x”7” out_1 4 x”7” in_2 4 x”2” in_3 Why do we need others here?

  9. std_logic, std_logic_vector Very common data types std_logic Single bit value Values: U, X, 0, 1, Z, W, H, L, - Example: signal A : std_logic; A <= ‘1’; Std_logic_vector: is an array of std_logic Example: signal A : std_logic_vector (4 downto 0); A <= x“00Z001”

  10. We will used counting events (e.g. part of MP2 as a motivating example) Detailed VHDL design exercises

  11. Streaming Network application (MP2) • Detect patterns in payload (e.g. “Corn!”) • Place the number of detections in last byte of payload FSM + Management logic

  12. Streaming Network application (MP2) • Detect patterns in payload (e.g. “Corn!”) • Place the number of detections in last byte of payload FSM + Management logic IP src

  13. Streaming Network application (MP2) IP dest IP src • Detect patterns in payload (e.g. “Corn!”) • Place the number of detections in last byte of payload FSM + Management logic

  14. Streaming Network application (MP2) src port IP dest IP src • Detect patterns in payload (e.g. “Corn!”) • Place the number of detections in last byte of payload FSM + Management logic

  15. Streaming Network application (MP2) dest port src port IP dest IP src • Detect patterns in payload (e.g. “Corn!”) • Place the number of detections in last byte of payload FSM + Management logic

  16. Streaming Network application (MP2) length dest port src port IP dest IP src • Detect patterns in payload (e.g. “Corn!”) • Place the number of detections in last byte of payload FSM + Management logic

  17. Streaming Network application (MP2) Data 1 length dest port src port IP dest IP src • Detect patterns in payload (e.g. “Corn!”) • Place the number of detections in last byte of payload FSM + Management logic

  18. Streaming Network application (MP2) Data 2 Data 1 length dest port src port IP dest IP src • Detect patterns in payload (e.g. “Corn!”) • Place the number of detections in last byte of payload FSM + Management logic

  19. Streaming Network application (MP2) Data 3 Data 2 Data 1 length dest port src port IP dest • Detect patterns in payload (e.g. “Corn!”) • Place the number of detections in last byte of payload FSM + Management logic

  20. Streaming Network application (MP2) Send Alert Data 3 Data 2 Data 1 length dest port src port IP dest • Detect patterns in payload (e.g. “Corn!”) • Place the number of detections in last byte of payload FSM + Management logic

  21. Streaming Network application (MP2) Send Alert r o C length dest port src port IP dest • Detect patterns in payload (e.g. “Corn!”) • Place the number of detections in last byte of payload FSM + Management logic

  22. Streaming Network application (MP2) Send Alert n r o C length dest port src port • Detect patterns in payload (e.g. “Corn!”) • Place the number of detections in last byte of payload FSM + Management logic

  23. Streaming Network application (MP2) Send Alert ! n r o C length dest port • Detect patterns in payload (e.g. “Corn!”) • Place the number of detections in last byte of payload FSM + Management logic

  24. Streaming Network application (MP2) Send Alert Modify Packet ! n r o C length dest port • Detect patterns in payload (e.g. “Corn!”) • Place the number of detections in last byte of payload FSM + Management logic

  25. Architecture • Detect patterns in payload (e.g. “Corn!”) • Place the number of detections in last byte of payload Draw out logic, and data flow!!! Alert FSM Alert Register & Counter Management Packet Length position output sel corn_cnt 2:1 Mux Packet Input Process Packet Output Process

  26. Architecture • Detect patterns in payload (e.g. “Corn!”) • Place the number of detections in last byte of payload Alert FSM Alert Register & Counter Management Packet Length position output sel corn_cnt 2:1 Mux Packet Input Process Packet Output Process

  27. Alert FSM Design • Alert signal when the pattern “corn!” is detected • Z = {Alert} “r”/0 “c”/0 “o”/0 “n”/0 c o r n ! others/0 Start others/0 others/0 others/0 “!”/1

  28. Alert FSM Design • Alert signal when the pattern “corn!” is detected • Output Packet’s Length • Z = {Alert,length_vld,pack_length} • X = {vld,input} : Note “?” is don’t care “r”/0 “c”/0 “o”/0 “n”/0 c o r n ! others/0 Start others/0 others/0 others/0 “!”/1

  29. Alert FSM Design • Alert signal when the pattern “corn!” is detected • Output Packet’s Length • Z = {Alert,length_vld,pack_length} • X = {vld,input} : Note “?” is don’t care UDP ports 1,“r”/0,0,0 1,“c”/0,0,0 1,“o”/0,0,0 1,“n”/0,0,0 1,”?”/0,0,0 1,”?”/0,0,0 c o r n ! IPH_5 UDP length 1,others/0,0,0 1,”?”/0,1,length IPH_2 1,others/0,0,0 1,others/0,0,0 1,”?”/0,0,0 1,others/0,0,0 Start IP 1,“!”/1,0,0 Start

  30. Architecture • Detect patterns in payload (e.g. “Corn!”) • Place the number of detections in last byte of payload Alert FSM Alert Register & Counter Management Packet Length position output sel corn_cnt 2:1 Mux Packet Input Process Packet Output Process

  31. Register & Counter Manager • Register & Counter Components • Design of Manager

  32. Register and Counter Components Register reset load sel(reset,load) 0 set_value 3:1 Mux reg_val 8 8 DFF Counter reset load inc sel(reset,load,inc) 0 set_value 4:1 Mux count 8 8 8 + inc_val DFF

  33. Practice: Write VHDL(process for each) Register Name : process(clk) begin if(clk’event and clk=‘1’) then logic here end if; end process Name reset load sel(reset,load) 0 reg_val 3:1 Mux 8 set_value 8 DFF CASE sel is WHEN “00” | “11”=> out_1 <= in_0; WHEN “01” => out_1 <= in_1; WHEN OTHERS => out_1 <= in_0; END CASE; Counter reset load inc sel(reset,load,inc) 0 set_value 4:1 Mux count 8 8 8 + inc_val DFF

  34. Register VHDL Name : process(clk) begin if(clk’event and clk=‘1’) then CASE reset&load is WHEN “10” | “11” => reg_val <= 0; WHEN “01” => reg_val <= set_value; WHEN OTHERS => reg_val <= reg_val; END CASE; end if; end process Name Register reset load sel(reset,load) 0 set_value 3:1 Mux reg_val 8 8 DFF

  35. Register VHDL Name : process(clk) begin if(clk’event and clk=‘1’) then CASE sel is WHEN “10” | “11” => reg_val <= 0; WHEN “01” => reg_val <= set_value; WHEN OTHERS => reg_val <= reg_val; END CASE; end if; end process Name sel <= reset&load; Register reset load sel(reset,load) 0 set_value 3:1 Mux reg_val 8 8 DFF

  36. Counter VHDL Name : process(clk) begin if(clk’event and clk=‘1’) then CASE reset&load&inc is WHEN “100” | “101” | “110”| “111” => count <= 0; WHEN “010” | “011” => count <= set_value; WHEN “001” => count <= count + inc_val; WHEN OTHERS => count <= count; END CASE; end if; end process Name Counter reset load inc sel(reset,load,inc) 0 set_value 4:1 Mux inc_val count 8 8 8 + DFF

  37. Counter VHDL Name : process(clk) begin if(clk’event and clk=‘1’) then CASE sel is WHEN “100” | “101” | “110”| “111” => count <= 0; WHEN “010” | “011” => count <= set_value; WHEN “001” => count <= count + inc_val; WHEN OTHERS => count <= count; END CASE; end if; end process Name sel <= reset&load&inc; Counter reset load inc sel(reset,load,inc) 0 set_value 4:1 Mux inc_val count 8 8 8 + DFF

  38. Architecture To count and insert counts into data flow we need a few more control signals Alert FSM Alert Register & Counter Management Packet Length position output sel corn_cnt 2:1 Mux Packet Input Process Packet Output Process

  39. Architecture • To count and insert counts into data flow we need a few more control signals Alert Alert FSM Register & Counter Management Packet Length reset length_vld reset position output sel Packet_length data data_vld corn_cnt 2:1 Mux Packet Input Process Packet Output Process

  40. Architecture Use the control signals and the modules we just built to implement the “Register & Counter” Management module. Alert Alert FSM Register & Counter Management Packet Length reset length_vld reset position output sel Packet_length data data_vld corn_cnt 2:1 Mux Packet Input Process Packet Output Process

  41. Register and Counter Manger (Exercise) Alert inc corn_cnt Counter inc_val load reset set_value reset inc position Counter Valid_data inc_val load reset set_value reset length_vld load Packet_Length_reg Register Packet_Length set_value

  42. Register and Counter Manger (Exercise) Alert inc corn_cnt Counter inc_val load reset set_value reset inc position Counter Valid_data inc_val load reset set_value reset length_vld load Packet_Length_reg Register Packet_Length set_value

  43. Register and Counter Manger Alert inc corn_cnt Counter inc_val 1 load 0 0 reset set_value reset inc position Counter Valid_data inc_val 1 load 0 0 reset set_value reset length_vld load Packet_Length_reg Register Packet_Length set_value

  44. Architecture • Detect patterns in payload (e.g. “Corn!”) • Place the number of detections in last byte of payload Alert Alert FSM Register & Counter Management Packet Length reset length_vld reset position output sel Packet_length data data_vld corn_cnt 2:1 Mux Packet Input Process Packet Output Process

  45. Architecture • Place the number of detections in last byte of payload Alert Alert FSM Register & Counter Management Packet Length reset length_vld reset position output sel Packet_length data data_vld corn_cnt 2:1 Mux Packet Input Process Packet Output Process

  46. Output sel Comparator outputs 1 if inputs match Packet_length Comparator Position sel corn_cnt 1 2:1 Mux Data_to_output Data_from_input 0

  47. Output sel: VHDL NOT in a process! Data_to_output <= corn_cnt when (Packet_length = Position) else Data_from_input Comparator outputs 1 if inputs match Packet_length Comparator Position sel corn_cnt 1 2:1 Mux Data_to_output Data_from_input 0

  48. Architecture • Detect patterns in payload (e.g. “Corn!”) • Place the number of detections in last byte of payload Alert Alert FSM Register & Counter Management Packet Length reset length_vld reset position output sel Packet_length data data_vld corn_cnt 2:1 Mux Packet Input Process Packet Output Process

  49. Modify corn! counter for Multiple matches Alert inc Counter corn_cnt inc_val 1 0 load 0 set_value reset reset

  50. Modify corn! counter for Multiple matches Alt_0 Alt_1 inc Alt_2 Counter Alt_3 corn_cnt inc_val 1 0 load 0 set_value reset reset

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