Circuit design with alternative energy efficient devices
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Circuit Design with Alternative Energy-Efficient Devices. Elad Alon Collaborators: Hei Kam, Fred Chen (MIT), Tsu-Jae King-Liu, Vladimir Stojanovic (MIT), Dejan Markovic (UCLA), Mark Horowitz (Stanford). Dept. of EECS, UC Berkeley. CMOS is Scaling, Power Can Not. 1000.

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Circuit Design with Alternative Energy-Efficient Devices

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Circuit design with alternative energy efficient devices

Circuit Design with Alternative Energy-Efficient Devices

Elad Alon

Collaborators: Hei Kam, Fred Chen (MIT), Tsu-Jae King-Liu, Vladimir Stojanovic (MIT), Dejan Markovic (UCLA), Mark Horowitz (Stanford)

Dept. of EECS, UC Berkeley


Cmos is scaling power can not

CMOS is Scaling, Power Can Not

1000

Predictions(ca. 2000)

Reality

(Core 2)

Itanium II

Itanium

100

Pentium 4

Pentium III

Pentium Pro

Power (W)

10

Pentium

Pentium II

486DX

80286

8086

8088

1

386DX

8080

8008

S. Borkar, Intel

4004

0.1

1970

1975

1980

1985

1990

1995

2000

2005

2010


Supply and threshold voltages

Supply and Threshold Voltages

kT/q doesn’t scale, so lowering Vth increases leakage

Fixed Vth, Vdd power density doesn’t scale well

Ed Nowak, IBM

Drain Current Id

Scaling Vth, Vdd

Gate Voltage Vg


Alternative devices to the rescue

Alternative Devices to the Rescue?

Many new devices withS-1<60mV/dec proposed

But, many of these are slow (low Ion)

And/or have other “weird”characteristics

Can these devices reduce energy? If so, at what performance?

Need to look at the circuits

MOSFET

Drain Current Id

New Device

Slope=S-1

Gate Voltage Vg


Outline

Outline

Energy-Performance Analysis

Circuit Design with Relays

Conclusions


Processor power breakdown

Processor Power Breakdown

  • Most components track performance vs. energy curves of logic

    • Control, Datapath, Clock

  • Use proxy circuit to examine tradeoffs


Proxy circuit for static logic

Proxy Circuit for Static Logic

Vdd

Vdd

Output

Input

0V

Ld stages

Switching activity factor = ,

Gate capacitance per stage = C

  • tdelay = LdCVdd/(2Ion)

  • Edyn+Eleak = αLdCVdd2 + LdIoffVddtdelay


Simple optimization rule

Simple Optimization Rule

Optimal Ion/Ioff Ld/α

Derived in CMOS

But holds for nearly all switching devices

Pleak/Pdyn ~constant

~30-50% across wide range of parameters

Nose and Sakurai


Using the rule to compare

Using the Rule to Compare

MOSFET

  • Match Ioff by adjusting “VT”

  • New device wins if: Ion,new(Vdd) > Ion,MOS(Vdd)

“New Device”

Energy

“New Device”

Drain Current Id

MOSFET

Vddx

Vddx

Performance

Gate Voltage Vg


What else matters variability

What Else Matters: Variability

  • Leakage:

    • E(Ioff) vs. E(Vth)

  • Delay:

    • Finite Ld

    • Cycle time set by worst-case


What else matters wires area

What Else Matters: Wires & Area

Vdd

Vdd

Output

Input

0V

Cw

Cw

Cw

Cw

  • Devices don’t drive just other devices

  • Need to look at extrinsic cap (wires) too

    • Especially if device has area overhead


Parallelism

Parallelism

Serial: Perf. f

Energy

“New Device”

Parallel: Perf.  2f, E/op ~const

MOSFET

Performance

  • If available, parallelism allows slower devices

    • Extends energy benefit to higher performance


Minimum energy

Minimum Energy

At low performance or high parallelism:

Lowest Vdd for required Ion/Ioff wins

Vdd,min Seff,Emin  Seff2

Drain Current Id

Seff-1

Normalized Energy/cycle

Lower Seff

Gate Voltage Vg

Vdd(V)


Example tunneling fet

Example: Tunneling FET

Band-to-band tunneling device

Steep transition (<60mV/dec) at low current

Low Ion(<~100μA)

Assume work function can be tuned

Gate

N

Drain

Source

Drain Current Id (A/mm)

P

Ion ≈A(Vgs+VT)exp[-B/(Vgs+VT)] [1]

[1]J. Chen et al., IEEE Electron Device Lett., vol. EDL-8, no. 11, pp. 515–517, Nov. 1987.

Gate Voltage Vg (V)


Energy performance tradeoff

Energy-Performance Tradeoff

30 stages

α=0.01

TFET

Energy (J)

MOSFET

Performance (GHz)

  • Competitive with subthreshold CMOS

    • TFETs promising below ~100MHz


Outline1

Outline

Energy-Performance Analysis

Circuit Design with Relays

Conclusions


Nano electro mechanical relay

Nano-Electro-Mechanical Relay

Based on mechanically making and breaking contact

No leakage, perfectly abrupt transition

Reliability is the key challenge

Gon

Conductance

Vrl

Vpi

Gate Voltage Vg [V]


Circuit design with relays

Circuit Design with Relays

CMOS delay set by electrical time constant

Distribute logical/electrical effort over many stages

Relay: mechanical delay (~10ns) >> electrical t (~1ps)

Implement logic as a single complex gate

CMOS:

Relay:


Relay energy perf tradeoff

Relay Energy-Perf. Tradeoff

Stack of 30 series relays

No leakage

Vdd,min set onlyby functionality(surface force)

How about real logic circuits?

TFET

MOSFET

Energy (J)

Relay

Performance (GHz)


Relay based adder

Relay-Based Adder

  • Manchester carrychain

  • Ripple carry

    • Cascade full adder cells

  • N-bit adder still 1 mechanical delay


Adder energy delay

Adder Energy-Delay

  • Compare vs. optimalCMOS adder

  • ~10-40x slower

    • Low Rcont not critical

  • ~10-100x lower E/op

    • Lower Cg

    • Fewer devices, all minimum size

    • Lower Vdd,min


Parallelism and area

Parallelism and Area

  • If parallelism available, can trade area for throughput

  • Competing with sub-threshold CMOS

    • Area-overhead bounded


Power breakdown revisited

Power Breakdown Revisited

  • Better logic  “uncore” power dominant

  • Need to analyze (and leverage) devices for entire system…

    • Relay DRAM or NVM (not SRAM)?

    • Relay ADC/DACs?


Outline2

Outline

Simple Energy-Performance Analysis

Circuit Design with Relays

Conclusions


Summary

Summary

  • New devices need circuit level analysis

    • Ion/Ioff set by logic depth, activity factor

    • Don’t forget about variability, wires

    • Tailor circuit style to the device

  • If available, parallelism may allow slower (low Ion) devices

    • Don’t forget about the rest of the system


Good news bad news

Good News/Bad News

Today:Parallelism lowers E/op

Future: Parallelism doesn’t help

-1

  • Parallelism still available in CMOS

    • But eventually limited by Emin

  • Opportunity for new devices…

    • At least in sub-100MHz applications


Acknowledgements

Acknowledgements

  • Berkeley Wireless Research Center

  • NSF

  • DARPA

  • FCRP


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