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Chapter 10: 68HC11 Serial Peripheral Interface

Chapter 10: 68HC11 Serial Peripheral Interface. The 68HC11 Microcontroller. Han-Way Huang. Minnesota State University, Mankato. Why SPI? - The number of I/O port pins are limited on an 8-bit microcontroller. - It is desirable to implement more I/O functions on the same number of port pins.

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Chapter 10: 68HC11 Serial Peripheral Interface

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  1. Chapter 10: 68HC11 Serial Peripheral Interface The 68HC11 Microcontroller Han-Way Huang Minnesota State University, Mankato

  2. Why SPI? - The number of I/O port pins are limited on an 8-bit microcontroller. - It is desirable to implement more I/O functions on the same number of port pins. - Many I/O devices do not require high speed. - SPI allows more I/O functions to be supported on the 68HC11. A Summary of the 68HC11 SPI System - Two types of devices are involved in data transfer in the SPI format: master and slaves - Multiple SPI compliant devices can be interconnected - The master device initiates data transfer and also generates the clock signal required for data transfer synchronization - The 68HC11 SPI is often used for I/O port expansion, and interfacing with peripheral devices such as LED/LCD display drivers, phase-locked loop chips, A/D and D/A converters, serial EEPROMs, serial SRAMs, etc.

  3. SPI Pins - SS/PD5: slave select - SCK/PD4: serial clock - MOSI/PD3: master out slave in - MISO/PD2: slave out master in

  4. SPI-Related Registers 1. The Serial Peripheral Control Register (SPCR) SPIE: SPI interrupt enable SPE: SPI enable DWOM: port D wired-or mode select MSTR: SPI master or slave select CPOL: clock polarity. 1: SCK idle high, 0: SCK idle low CPHA: SCK clock phase. Control the clock-data relationships between the master and slave. CPHA and CPOL must be used together. See Figure 9.1. SPR1 & SPR0: SPI clock rate select

  5. Serial Peripheral Status Register (SPSR) Port D Data Direction Register (DDRD)

  6. SPICircuit Connection 1. Single master single slave

  7. 2. SPI Single master and multiple slaves circuit connection I - The SPI master can selectively exchange data with any slave. - By disconnecting the MISO pin, the master can output data to one or multiple slaves at the same time.

  8. 3. SPI Single master and multiple slaves circuit connection II - All slaves are connected into a large shift register chain. - The master cannot selectively exchange data with a single slave.

  9. SPI Data Transfer 1. The procedure - An SPI transfer is initiated by writing data to the shift register in the master SPI device. - Data is circuited 8 bit positions; thus data is exchange between the master and the slave. - The master SPI device sends out 8 pulses from the SCK pin to synchronize data transfer. - After 8 bits have been transferred, the SPIF flag of the SPSR register will be set to 1. 2. Error conditions - write collision: a write is performed during an SPI data transfer. The write will be unsuccessful and the WCOL bit of the SPSR register will be set to 1. - mode fault: the SS input of a master is asserted low. The SPI master that has a mode fault will: (1) generate an SPI interrupt if SPIE = 1 (2) clear SPE flag to disable the SPI (3) clear the MSTR bit forcing itself into the slave mode (4) force the DDRD bits to zeros for the four SPI pins.

  10. 3. The program to transfer data from the master to a slave regbas equ $1000 ; base address of the I/O register block SPDR equ $2A ; offset of SPDR from regbas SPCR equ $28 ; offset of SPCR from regbas SPSR equ $29 ; offset of SPSR from regbas DDRD equ $09 ; offset of DDRD from regbas SPI_DIR equ $38 ; value to set SS, SCK and MOSI pins for output and MISO for input SPI_INI equ $54 ; value to initialize the SPI which will enable SPI, disable SPI * ; interrupt, configure port D pins as normal CMOS pins, select * ; master mode, choose the falling edge of SCK to shift data, and * ; sets data rate to 1 Mbits/sec at 2 MHz E clock ORG $00 data RMB $10 ; a data buffer . . ldx #regbas ldaa #SPI_DIR staa DDRD,X ; set port D directions ldaa #SPI_INI staa SPCR,X ; initialize the SPI operation parameters ldaa data staa SPDR,X ; start SPI transfer wait ldab SPSR,X ; wait for data to be sent out bpl wait ; “ . .

  11. 3. The program to read data from a slave ldx #regbas ldaa #SPI_DIR staa DDRD,X ldaa #SPI_INI staa SPCR,X staa SPDR,X ; start an SPI transfer here ldab SPSR,X ; wait until 8 bits have been shifted in bpl here ; “ ldaa SPDR,X ; place the byte in A . . .

  12. Simulating the SPI If data is shifted on the falling edge of the clock signal: Step 1: Set the clock to high. Step 2: Apply the data bit on the port pin that is connected to the serial data input pin of the peripheral device. Step 3. Pull the clock to low. Step 4. Repeat steps 1 to 3 for as many times as needed. If the rising edge is used to shift data, then - set clock to low in step 1 - set clock to high in step 3

  13. Shift register HC589

  14. HC589 Operation 1. The parallel data inputs (A,…,H) will be loaded into the data latch on the rising edge of the latch clock. 2. When the serial shift/parallel load signal is low, the data in the data latch will be loaded into the shift register. Otherwise, the shift register is enabled to shift. 3. When the shift register is enabled to shift, the serial data input SA will be shifted into the shift register and the data on stage H will be shifted out from pin QH. 4. The output enable signal (pin 10) must be low in order for data at stage H be driven out from pin QH. Application of HC589 - to expand the number of parallel input ports of 8-bit microcontrollers. - convert parallel data into serial format

  15. Interfacing the HC589 to the SPI Method 1.

  16. Method I (continued) procedure for data transfer: Step 1. Program the DDRD register to configure SCK, TxD, and SS pins for output and the MISO pin for input. Step 2. Program the SPCR register to enable the SPI function and set up other parameters. Step 3. Set the LC pin to low and then pull it to high; this will load the external data into the data latch in parallel. Step 4. Set the SS pin to low to select the parallel load mode, which will load the contents of the data latch into the shift register. Step 5. Set the SS pin to high to select the serial shift mode. Step 6. Write a byte into the SPDR register to trigger eight SCK clock pulses to shift in 8 bits. Step 7. Repeat step 6 as many times as needed, and save the data in a buffer.

  17. Example 10.1 Write a program to input 8 bytes from 8 external HC589s connected as shown in Figure 10.6 and store the data at locations $00-$07. Solution: Configure the SS, SCK, MOSI, and TxD pins for output and MISO and RxD pins for input -- write the value %00111010 ($3A) into DDRD. Write the value %01010000 ($50) into the SPCR register to: 1. disable SPI interrupt 2. enable the SPI 3. set port D pins for normal CMOS output pins (not open drain) 4. use the rising edge of the SCK signal to shift data 5. select a 1-Mbits/sec data rate regbas equ $1000 PORTD equ $08 DDRD equ $09 SPCR equ $28 SPSR equ $29 SPDR equ $2A SPCR_INI equ $50 SPI_DIR equ $3A

  18. org $C000 ldx #regbas ldaa #SPI_DIR staa DDRD,X ; configure SPI pin directions ldaa #SPCR_INI staa SPCR,X ; initialize SPI operation parameters * The following two instructions load data into HC589s in parallel bclr PORTD,X $02 ; pull TxD (LC) to low bset PORTD,X $02 ; pull TxD (LC) to high bclr PORTD,X $20 ; pull SS pin to low to select parallel load mode and load ; the contents of the data latch into the shift register bset PORTD,X $20 ; pull SS pin to high to select serial shift mode ldab #8 ; loop count for transferring 8 bytes ldy #$0000 ; set Y to point to the buffer loop staa SPDR,X ; trigger SPI data transfer brclr SPSR,X $80 * ; wait until 8 bits have been shifted ldaa SPDR,X ; get one byte staa 0,Y ; save the data decb ; decrement loop count bne loop end

  19. In C language, #include <hc11.h> main ( ) { char buffer[8], i; DDRD = 0x3A; /* configure port D pins directions */ SPCR = 0x50; /* configure SPI parameters */ PORDT &= 0xFD; /* create a rising edge on the TxD pin */ PORTD |= 0x02; /* to load data into data latch */ PORTD &= 0xDF; /* transfer data from data latch to shift register */ PORTD |= 0x20; /* select serial shift mode */ for (i = 0; i < 8; i++) { SPDR = 0x00; /* shift data in from the MISO pin */ while (!(SPSR & 0x80)); /* wait for data to shift in */ buffer [i] = SPDR; } return 0; }

  20. Interfacing the HC589 to the SPI -- Method II

  21. Procedure for data transfer(method II) Step 1. Program the DDRD register to set the directions of the MISO, SCK, SS, and TxD pins. Step 2. Program the SPCR register to configure the SPI operation parameters. Step 3. Set the TxD pin to low and then pull it to high to load external data into the data latch in parallel. Step 4. Set the SS pin to low to select the parallel load mode, which will load the contents of the data latch into the shift register. Step 5. Pull the SS pin to high to select the serial shift mode. Step 6. Set the port B that controls the specified HC589 to low to enable the shift register to output serial data. The remaining port B pins are set to high. Step 7. Write a byte into the SPDR register to trigger eight pulses from the SCK pin to shift in the serial data. The external data is now in the SPDR register and ready for use. Step 8. Repeat steps 6 and 7 as many times as needed.

  22. Shift Register HC595

  23. HC595 Operation - The shift register accepts serial data and provides a serial output. - The serial data input (A) is shifted into the shift register on the rising edge of the shift clock. - The data in the shift register will be loaded into the output latch on the rising edge of the latch clock. - A low on the output enable pin allows data from the latch to be presented at the output pins QA-QH. - The serial output SQH does not have tri-state capability. - Multiple HC595s can be cascaded to expand the number of parallel output ports for the 68HC11.

  24. Interfacing HC595 to the SPI -- Method I

  25. Method I (continued) Data transfer procedure Step 1. Program the DDRD register to configure SPI pin directions. Step 2. Program the SPCR register to set up appropriate SPI operating parameters. Step 3. Write a byte into the SPDR register to trigger eight pulses from the SCK pin. Step 4. Repeat step 3 as many times as needed. Step 5. Set the SS pin to low and then pull it to high to transfer the byte in the shift register into the output latch. After this step, the output latch contains valid data. Example 9.2 Write a program to output three bytes to the first three HC595s in Figure 9.8. Solution: regbas equ $1000 PORTD equ $08 DDRD equ $09 SPCR equ $28 SPDR equ $2A SPSR equ $29

  26. SPI_DIR equ $3A ; value to configure SPI pin directions SPCR_IN equ $50 ; value to enables SPI, disables SPI interrupt, chooses rising * ; edge of SCK to shift data, selects normal port D pins, * ; and sets data rate to 1 Mbits/sec. K equ 3 org $00 buffer fcb $11,$22,$33 org $C000 ldx #regbas ldaa #SPI_DIR staa DDRD,X ; configure pins SS, MOSI, SCK, and TxD for output ldaa #SPCR_IN staa SPCR,X ; configure SPI operation parameters ldab #K ; set up loop count ldy #buffer ; set Y as a pointer to the buffer ch_loop ldaa 0,Y ; send out one byte via SPI function staa SPDR,X ; “ brclr SPSR,X $80 * ; wait until the byte is shifted out iny ; move the buffer pointer decb ; decrement the loop count bne ch_loop bclr PORTD,X $20 ; create a rising edge on SS pin to load data into output bset PORTD,X $20 ; latch end

  27. Interfacing the HC595 to the SPI -- Method II

  28. Method II: Data transfer procedure Step 1. Program the DDRD register to set up SPI pin directions. Step 2. Program the SPCR register to enable the SPI subsystem, select the data rate, select the rising edge of SCK signal for data shifting, select master mode, and disable interrupt. Step 3. Write a byte into SPDR to trigger SPI data transfer. Step 4. Set the PBi pin to low and then pull it to high to load the byte from the shift register of the HC595 i into its output latch.

  29. The Seven-Segment Display Driver Chip MC14489

  30. MC14489 Pins Data In: A serial data input pin. Clock: The rising edge of this signal is used to shift data into the shift register. The highest shift clock frequency is 4 MHz. Enable: External data can be entered when this signal is low. The data are loaded from the shift register into the latches on the rising edge of this signal. a thru h: Seven-segment outputs for driving seven segments and decimal point LEDs. Bank 1..5: Digit select pins. The MC14489 can drive up to five seven-segment displays, but only one seven-segment display is lighted at any time. The display to be lighted is selected by these pins. Rx: External current-setting resistor. The relationship between the segment current and Rx is shown in Figure 10.12.

  31. The MC14489 Operation - The configuration register controls the MC14489 operation. - Two operation modes: hex mode and special decode. The decode function is shown in Table 10.1. - Displays can be made dimmer or brighter by clearing or setting the first bit of the display data sent to the MC14489.

  32. Interfacing the MC14489 to the 68HC11 SPI

  33. - One byte of configuration information and 3 bytes of display data must be sent to the MC14489 in Figure 10.14. - The 4 most significant bits control the brightness and display of h segments as shown in Figure 10.15.

  34. Example 10.3 Write a program to display 997.04 from bank 5 to bank 1 in Figure 10.14. Use the normal brightness to display these five digits. Solution: The control byte to be written into the configuration register is as follows: bit 7: no decode, set to 0 bit 6: no decode, set to 0 bit 5: bank 5 hex decode, set to 0 bit 4: bank 4 hex decode, set to 0 bit 3: bank 3 hex decode, set to 0 bit 2: bank 2 hex decode, set to 0 bit 1: bank 1 hex decode, set to 0 The display data format is

  35. The Configuration of SPCR register: bit 7 (SPIE): set to 0 to disable interrupt bit 6 (SPE): set to 1 to enable SPI function bit 5 (DWOM): set to 0 to choose normal port D pins bit 4 (MSTR): set to 1 to select master mode bit 3 & 2 (CPOL & CPHA): set to 00 to use rising edge to shift data out bit 1 & 0 (SPR1 & SPR0): set to 00 to choose 1 MHz shift rate regbas equ $1000 PORTD equ $08 DDRD equ $09 SPCR equ $28 SPDR equ $2A SPSR equ $29 SP_DIR equ $3A ; value to configure SPI pins directions SPCR_IN equ $50 ; value to set up the specified SPI operation parameters

  36. ORG $00 disp_dat FCB $B9,$97,$04 ORG $C000 LDX #regbas LDAA #SP_DIR STAA DDRD,X ; configure SPI pin directions LDAA #SPCR_IN STAA SPCR,X ; initialize the SPI parameters BCLR PORTD,X $20 ; enable data shifting to MC14489 LDAA #$01 STAA SPDR,X ; send out configuration data to MC14489 BRCLR SPSR,X $80 * ; wait until configuration data has been shifted out BSET PORTD,X $20 ; latch data into configuration register BCLR PORTD,X $20 ; enable SPI data transfer to MC14489 LDY #disp_dat LDAB #3 loop LDAA 0,Y STAA SPDR,X BRCLR SPSR,X $80 * INY DECB BNE loop BSET PORTD,X $20 ; load data into display data register END

  37. A C Program for Sending Data to MC14489 #include <hc11.h> main ( ) { int i; unsigned char disp_dat[3] = {0xB9, 0x97, 0x04}; DDRD = 0x3A; SPCR = 0x50; PORTD &= 0xDF; /* enable SPI data transfer to MC14489 */ SPDR = 0x01; /* send out configuration data */ while (!(SPSR & 0x80)); /* wait until data have been shifted out */ PORTD |= 0x20 /* load data into configuration register */ PORTD &= 0xDF; /* enable SPI transfer to MC14489 */ for (i = 0; i < 3; i++) { SPDR = disp_dat [i]; while (!(SPSR & 0x80)); } PORTD |= 0x20; } /* load data into display data register */

  38. Cascading MC14489s - Connect the Data Out pin of one MC14489 to the Data In pin of the next MC14489. - To configure n MC14489s, we need to send out 3 × (n -1) + 1 bytes of data to the MC14489s. Only n bytes are used to configure the MC14489s. - A circuit of cascading three MC14489s is illustrated in Figure 10.17.

  39. Three bytes of configuration data must be sent to three MC14489s: Example 10.8 Write a program to display the following information (temperature at 14:20 of Aug. 2nd, 1999) on the 15 seven-segment displays driven by three MC14489s as shown in Figure 10.17: 30.5oC 14 20 08 02 99 Solution: - Use the special decode of character F to represent the character for degree. - Represent all other characters using normal decode method. - The left-most five digits are displayed by the MC14489 #1. - The middle five digits are displayed by the MC14489 #2. - The right-most five digits are displayed by the MC14489 #3.

  40. Configurations of three MC14489s MC14489 #1: C7: set to 0 to select no decode C6: set to 1 to select special decode (display degree character on bank 2) C5..C3: set to 0 to select hex decode C2: set to 1 to select special decode C1: set to 0 to select hex decode C0: set to 1 to select normal mode MC14489 #2 & #3: C7 & C6: set to 0 to select no decode C5..C1: set to 0 to select hex decode C0: set to 1 to select normal mode - The configuration data for the MC14489 #3 should be sent out first. - The complete configuration data is 01xxxx01xxxx45, where x strands for don’t care and should be set to 0.

  41. Display Data for MC14489 #1 Display Data for MC14489 #2 Display Data for MC14489 #3

  42. REGBAS EQU $1000 SPSR EQU $29 SPDR EQU $2A SPCR EQU $28 PORTD EQU $08 DDRD EQU $09 ORG $C000 LDX #REGBAS LDAA #$3A STAA DDRD,X ; configure SPI pin directions LDAA #$50 STAA SPCR,X ; configure SPI parameters LDAB #7 BCLR PORTD,X $20 ; enable SPI transfer to MC14489s LDY #conf_dat ; set Y to point to configuration data loop1 LDAA 0,Y STAA SPDR,X BRCLR SPSR,X $80 * ; wait until a byte has been shifted out INY DECB BNE loop1 BSET PORTD,X $20 ; load data into configuration registers

  43. BCLR PORTD,X $20 ; enable SPI transfer to MC14489s LDY #disp_dat LDAB #9 loop2 LDAA 0,Y STAA SPDR,X BRCLR SPSR,X $80 * INY DECB BNE loop2 BSET PORTD,X $20 ; load data into display data register … ; do something else conf_dat DB $01,$00,$00,$01,$00,$00,$45 disp_dat DB $88,$02,$99,$81,$20,$00,$C2,$55,$FC

  44. In C language #include <hc11.h> main ( ) { int i; unsigned char conf_dat [ ] = {0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x45}; unsigned char disp_dat [ ] ={0x88, 0x02, 0x99, 0x81, 0x20, 0x00, 0xC2, 0x55, 0xFC}; DDRD = 0x3A; SPCR = 0x50; PORTD &= 0xDF; /* enable SPI transfer to MC14489s */ for (i = 0; i < 7; i++) { SPDR = conf_dat[i]; while (!(SPSR & 0x80)); } PORTD |= 0x20; /* load data into configuration registers */ PORTD &= 0xDF; /* enable SPI transfer to MC14489s */ for (i = 0; i < 9; i++) { SPDR = disp_dat [i]; while (!(SPSR 7 0x80)); } PORTD |= 0x20; /* load data into display data registers */ return 0; }

  45. Liquid Crystal Displays (LCDs) - LCDs are often multiplexed to save connection pins. - Motorola has LCD drivers that drives 1/4 multiplexing LCDs. - In a 1/4 multiplexing LCD, each character is represented by a multiple of four segments. - An LCD display that displays BCD digit consists of seven segments and an optional decimal point. - An LCD segment is turned on and off by controlling the backplane and frontplane voltages. - Each BCD digit is controlled by two frontplane and four backplane signals. - There is no standard for backplane and frontplane connections on multiplexed LCD displays.

  46. The MC145000 and MC145001 LCD drivers

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