Cse 311 foundations of computing i
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CSE 311 Foundations of Computing I. Lecture 25 Circuits for FSMs, Carry-Look-Ahead Adders Autumn 2011. Announcements. Nice overview of adder circuits at http://www.aoki.ecei.tohoku.ac.jp/arith/mg/algorithm.html. Last lecture highlights. Languages not recognized by any DFA

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CSE 311 Foundations of Computing I

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Cse 311 foundations of computing i

CSE 311 Foundations of Computing I

Lecture 25

Circuits for FSMs, Carry-Look-Ahead Adders

Autumn 2011

CSE 311


Announcements

Announcements

  • Nice overview of adder circuits at

    http://www.aoki.ecei.tohoku.ac.jp/arith/mg/algorithm.html

CSE 311


Last lecture highlights

Last lecture highlights

  • Languages not recognized by any DFA

    • { 0n1n : n≥0 }

    • Binary Palindromes

    • Strings of Balanced Parentheses

  • Using DFAs for efficient pattern matching

CSE 311


Fsms in hardware

FSMs in Hardware

  • Encode the states in binary: e.g. states 0,1,2,3 represented as 000,100, 010,001, or as 00,01,10,11.

  • Encode the input symbols as binary signals

  • Encode the outputs possible as binary signals

  • Build combinational logic circuit to compute transition function:

Boolean Circuit for State Transition Function

current state

next state

output signals

input signals

CSE 311


Fsms in hardware1

FSMs in Hardware

  • Combine with sequential logic for

    • Registers to store bits of state

    • Clock pulse

  • At start of clock pulse, current state bits from registers and input signals are released to the circuit

  • At end of clock pulse, output bits are produced and next state bits are stored back in the same registers

Boolean Circuit for State Transition Function

current state

next state

output signals

input signals

CSE 311


Fsm for binary addition

FSM for binary addition

  • Assume that the two integers are an-1...a2a1a0 and bn-1...b2b1b0 and bits arrive together as [a0,b0] then [a1,b1] etc.

s

[0,0]

[1,1]

[0,1],[1,0]

[1,1]

[1,1]

[0,1],[1,0]

[1,1]

Cout=0

0

Cout=0

1

Cout=1

0

Cout=1

1

[0,0]

[0,0]

[0,1],[1,0]

[0,0]

[0,1],[1,0]

[0,1],[1,0]

[1,1]

[1,1] Generate a carry of 1

[0,1],[1,0] Propagate a carry of 1 if it was already there

[0,0]


Fsm for binary addition using output on edges

FSM for binary addition using output on edges

  • Assume that the two integers are an-1...a2a1a0 and bn-1...b2b1b0 and bits arrive together as [a0,b0] then [a1,b1] etc.

[0,0]:0

[1,1]:1

[1,1]:0

Cout=0

Cout=1

[0,0]:1

[0,1],[1,0]:1

[0,1],[1,0]:0

[1,1] Generate a carry of 1

[0,1],[1,0] Propagate a carry of 1 if it was already there


Example 1 bit full adder

Example: 1-bit Full Adder

A

B

input signals

1-Bit Full Adder

current state

next state

Cin

Cout

output

Sum

CSE 311


Fsms without sequential logic

FSMs without sequential logic

  • What if the entire input bit-strings are available at all once at the start?

    • E.g. 64-bit binary addition

  • Don’t want to wait for 64 clock cycles to compute the output!

  • Suppose all input strings have length n

    • Can chain together n copies of the state transition circuit as one big combinational logic circuit

CSE 311


A 2 bit ripple carry adder

A 2-bit ripple-carry adder

a

b

a0

b0

a1

b1

1-Bit Full Adder

Cin

Cout

Cin

Cout

0

Cin

Cout

Sum0

Sum1

Sum

CSE 311


Problem with chaining transition circuits

Problem with Chaining Transition Circuits

  • Resulting Boolean circuit is “deep”

  • There is a small delay at each gate in a Boolean circuit

    • The clock pulse has to be long enough so that all combinational logic circuits can be evaluated during a single pulse

    • Deep circuits mean slow clock.

CSE 311


Speeding things up

Speeding things up?

  • To go faster, need to work on both 1st half and 2nd half of the input at once

    • How can you determine action of FSM on 2nd half without knowing state reached after reading 1st half?

b1b2...bn/2 bn/2+1 ...bn-1bn

what state?

  • Idea: Figure out what happens in 2nd half for all possible values of the middle state at once

CSE 311


Transition function composition

Transition Function Composition

Transition table gives a function for each input symbol

f0

f1

0

0

0

0

s0

s1

s2

s3

State reached on input b1...bnis

fbn(fbn-1...(fb2(fb1(start)))...)= fbn∘ fbn-1...∘ fb2∘ fb1(start)

1

1

1

1

1

1

s0

s1

s2

s3

s0

s1

s2

S3

0

0

0

0,1

1

CSE 311


Transition function composition1

Transition Function Composition

b1

b2

b3

b4

b5

b6

b7

b8

  • Constant size 2-level

  • Boolean logic to

  • convert input symbol to

  • bits for transition function

  • compute composition of

  • two transition functions

  • Total depth 2 log2n

  • and size ≈n

fb1

fb2

fb3

fb4

fb5

fb6

fb7

fb8

f

g

fb2∘fb1

fb4∘fb3

fb6∘fb5

fb8∘fb7

g∘f

b

fb4∘fb3∘fb2∘fb1

fb8∘fb7∘fb6∘fb5

fb

fb8∘fb7∘fb6∘fb5∘fb4∘fb3∘fb2∘fb1

CSE 311


Carry look ahead adder

Carry-Look-Ahead Adder

Compute generate Gi= ai ∧ bi [1,1] propagate Pi=ai⊕ bi [0,1],[1,0]

These determine transition and output functions

  • Carry Ci=Gi∨ (Pi∧ Ci-1 ) also written Ci=Gi+PiCi-1

  • Sumi = Pi⊕ Ci-1

    Unwinding, we get

    C0=G0 C1=G1+G0P1 C2=G2+G1P2+G0P1P2

    C3=G3+G2P3+G1P2P3+G0P1P2P3

    C4=G4+G3P4+G2P3P4+G1P2P3P4+G0P1P2P3P4

    etc.

CSE 311


Carry look ahead adder1

Carry-Look-Ahead Adder

Compute all generate Gi= ai ∧ bi [1,1] propagate Pi=ai⊕ bi [0,1],[1,0]

Then compute all:

C0=G0 C1=G1+G0P1 C2=G2+G1P2+G0P1P2

C3=G3+G2P3+G1P2P3+G0P1P2P3

C4=G4+G3P4+G2P3P4+G1P2P3P4+G0P1P2P3P4 etc.

Finally, use these to compute

Sum0 = P0 Sum1 = P1⊕ C0Sum2 = P2⊕ C1 Sum3 = P3⊕ C2 Sum4 = P4⊕ C3 Sum5 = P5⊕ C4 etc

If all Ci are computed using 2-level logic, total depth is 4.

CSE 311


Adders using composition

Adders using Composition

Carry-look-ahead circuit for carry Cn-1 has 2 + 3 +...+ n = (n+2)(n-1)/2 gates

  • a lot more than ripple-carry adder circuit.

    Composition: (G,P) followed by (G’,P’) gives the same effect as (G’’,P’’) where

  • G’’= G’ ∨ (G ∧ P’) and P’’= P’ ∧ P also written as

    G’’= G’+G P’ and P’’= P’P

Composition gives an alternative approach

CSE 311


Adders using composition1

Adders using Composition

Composition: (G,P) followed by (G’,P’) gives the same effect as (G’’,P’’) where

  • G’’= G’ ∨ (G ∧ P’) and P’’= P’ ∧ P also written as

    G’’= G’+G P’ and P’’= P’P

    Use this for the circuit component in transition function composition tree

  • Computes Cn-1 in depth 2 log2 n and size ≈n

  • But we need all of C0, C1, ..., Cn-1 not just Cn-1

  • CSE 311


    Transition function composition2

    Transition Function Composition

    b0

    b1

    b2

    b3

    b4

    b5

    b6

    b7

    • Constant size 2-level

    • Boolean logic to

    • convert input symbol to

    • bits for transition function

    • compute composition of

    • two transition functions

    • Total depth 2 log2n

    • and size ≈n

    fb0

    fb1

    fb2

    fb3

    fb4

    fb5

    fb6

    fb7

    f

    g

    fb1∘fb0

    fb3∘fb2

    fb5∘fb4

    fb7∘fb6

    g∘f

    b

    fb3∘fb2∘fb1∘fb0

    fb7∘fb6∘fb5∘fb4

    fb

    fb7∘fb6∘fb5∘fb4∘fb3∘fb2∘fb1∘fb0

    CSE 311


    Computing all the values

    Computing all the values

    • We need to compute all of

      fb7∘fb6∘fb5∘fb4∘fb3∘fb2∘fb1∘fb0 Already computed

      fb6∘fb5∘fb4∘fb3∘fb2∘fb1∘fb0=fb6∘(fb5∘fb4)∘(fb3∘fb2∘fb1∘fb0)

      fb5∘fb4∘fb3∘fb2∘fb1∘fb0= (fb5∘fb4) ∘ (fb3∘fb2∘fb1∘fb0)

      fb4∘fb3∘fb2∘fb1∘fb0=fb4∘(fb3∘fb2∘fb1∘fb0 )

      fb3∘fb2∘fb1∘fb0Already computed

      fb2∘fb1∘fb0=fb2∘ (fb1∘fb0)

      fb1∘fb0Already computed

      fb0 Already computed

    CSE 311


    Parallel prefix circuit

    Parallel Prefix Circuit

    • The general way of doing this efficiently is called a parallel prefix circuit

      • Designed and analyzed by Michael Fischer and Richard Ladner (University of Washington)

    • Uses the adder composition operation that sets G’’= G’+G P’ and P’’= P’P

      • we just show it for the part for computing P’’ which is a Parallel Prefix AND Circuit

    CSE 311


    The parallel prefix and circuit

    The Parallel Prefix AND Circuit

    n/2 AND gates

    per level

    log2n levels

    Parallel Prefix

    n inputs

    Pn

    Parallel Prefix

    n/2 inputs

    P1P2...Pn

    Pn/2+1

    P1P2...Pn/2Pn/2+1

    P1P2...Pn/2

    Pn/2

    Parallel Prefix

    n/2 inputs

    P1P2

    P1

    P1


    Parallel prefix adder

    Parallel Prefix Adder

    • Circuit depth 2 log2 n

    • Circuit size 4 n log2 n

    • Actual adder circuits in hardware use combinations of these ideas and more but this gives the basics

    • Nice overview of adder circuits at

      http://www.aoki.ecei.tohoku.ac.jp/arith/mg/algorithm.html

    CSE 311


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