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CHAPTER 4

CHAPTER 4. Master Figure. Fig. 4.1. Figs. 4.2 a, b, c. ON PACKAGE. ON CHIP. Fig. 4.3. Fig. 4.4. Fig. 4.5. Fig. 4.6. Fig. 4.7. Fig. 4.8. Fig. 4.9. Port 1. Port 1. Port 1. Port 1. Top Electrode. Top Electrode. LCP. LCP. Bottom Electrode. Port 2. Port 2. Prepreg. Prepreg.

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CHAPTER 4

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  1. CHAPTER 4

  2. Master Figure

  3. Fig. 4.1

  4. Figs. 4.2 a, b, c

  5. ONPACKAGE ON CHIP Fig. 4.3

  6. Fig. 4.4

  7. Fig. 4.5

  8. Fig. 4.6

  9. Fig. 4.7

  10. Fig. 4.8

  11. Fig. 4.9

  12. Port 1 Port 1 Port 1 Port 1 Top Electrode Top Electrode LCP LCP Bottom Electrode Port 2 Port 2 Prepreg Prepreg Ground Plane Ground Plane Port 2 Port 2 Fig. 4.10

  13. Fig 4.11

  14. Figs. 4.12 a, b (b) (a)

  15. Lf Cf Cc C1 C2 Lc Ca La La Ca Cb Cb Lb Lb Fig. 4.13

  16. Fig. 4.14

  17. Fig. 4.15

  18. Cb Lb La Current Flow Lc Port 1 Port 2 Cc Cf Fig. 4.16

  19. Outputs Outputs Input Input Fig. 4.17

  20. d d d Z Z Z ab ab ab Z Z Z Z Z Z in in in load load load Z Z Z a a a Fig. 4.18

  21. Fig. 4.19

  22. Fig. 4.20

  23. C C C L L L Port 2 Port 2 Port 2 Port 1 Port 1 Port 1 L L L Port 3 Port 3 Port 3 C C C Fig. 4.21

  24. Fig. 4.22

  25. Fig. 4.23

  26. Fig. 4.24

  27. Fig. 4.25

  28. Fig. 4.26

  29. Fig. 4.27 S12 S13

  30. Fig. 4.28

  31. Fig. 4.29

  32. Fig. 4.30

  33. Fig. 4.31

  34. HF (in dB) Fig. 4.32

  35. Fig. 4.33

  36. Figs. 4.34 a, b

  37. Fig. 4.35

  38. Fig. 4.36

  39. Fig. 4.37

  40. 1.79 GHz 1.79 GHz 1.79 GHz P P P = = = - - - 1 dBm 1 dBm 1 dBm out out out 0.9 GHz 0.9 GHz 0.9 GHz a a P P P = +1 dBm = +1 dBm = +1 dBm out out out Res BW 3Mhz VBW 3 Mhz Sweep 265 ms (401 pts) b b Figs. 4.38 a, b

  41. HBFP 0420 GSG pads GSG pads Fig. 4.39

  42. Fig. 4.40

  43. Fig. 4.41

  44. Fig. 4.42

  45. Fig. 4.43

  46. Digital Digital Analog Analog Output Output Input Input I(s) I(s) I(s) I(s) I(s) I(s) I(s) I(s) + + + + + + + + + + g0 g0 g1 g1 g3 g3 g4 g4 - - - - - - - - - - LEVEL 1 LEVEL 1 Architectural Level Architectural Level + + + + g2 g2 g5 g5 Behavior Simulation Behavior Simulation a1 a1 a2 a2 a5 a5 a4 a4 a3 a3 System Level Block Diagram of a 4th Order Delta - Sigma A/D LEVEL 2 LEVEL 2 Transistor Level Circuit Transistor Level Circuit SPICE Simulation SPICE Simulation Transistor Level Circuit Schematic of a Transconductance Amplifier LEVEL 3 LEVEL 3 Physical Layout Physical Layout EM and SPICE Simulation EM and SPICE Simulation Physical Layout of the Transconductance Amplifier Above Fig. 4.44

  47. C_resn1 C_resn1 C_resn2 C_resn2 L_cp CC CC C_m2 C_m2 C_m1 C_m1 L1 L1 L2 L2 Fig. 4.45

  48. Fig. 4.46

  49. Fig. 4.47

  50. Figs. 4.48 a, b (a) (b)

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