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CPRE 583 Reconfigurable Computing Lecture 7: 9/14/2011 (Common VHDL Mistakes: “It works perfect in simulation, but not in the hardware!” ). Instructor: Dr. Phillip Jones (phjones@iastate.edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA.
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CPRE 583Reconfigurable Computing Lecture 7: 9/14/2011(Common VHDL Mistakes: “It works perfect in simulation, but not in the hardware!” ) Instructor: Dr. Phillip Jones (phjones@iastate.edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http://class.ece.iastate.edu/cpre583/
Announcements/Reminders • MP1: Due Next Friday. We will push MP2 back a week and cut it from 3 weeks to 2 weeks • Mini literary survey assigned • PowerPoint tree due: Fri 9/23 by class, so try to have to me by 9/22 night. My current plan is to summarize some of the classes findings during class. • Final 5-10 page write up on your tree due: Fri 9/30 midnight.
Start with searching for papers from 2007-2010 on IEEE Xplorer: http://ieeexplore.ieee.org/ Advanced Search (Full Text & Meta data) Find popular cross references for each area For each area try to identify 1 good survey papers For each area Identify 2-3 core Problems/issues For each problem identify 2-3 Approaches for addressing For each approach identify 1-2 papers that Implement the approach. Literary Survey
Literary Survey: Example Structure Hardware Accelerated Bioinformatics P2 P3 P1 A1 A2 A3 A1 A2 A1 A2 I1 I1 I1 I2 I1 I1 I2 I1 I1 • 5-10 page write up on your survey tree
Overview • Common VHDL mistakes • What you should learn • What are the ~6 common mistakes • How to identify these mistakes • How to fix these mistakes
My design works in simulation, but not in hardware!! • Clocked and non-clock processes common issues. • Clean Statemachine design, using best know practices • Common Mistakes pdf document
Clocked vs. non-clock processes Clocked process (clock is ONLY in the sensitivity list) Non-clocked process (clock is NOT in the sensitivity list) process (clk) begin -- check for rising edge of the clk if(clk’event and clk = ‘1’) then -- initialize all driven signals during reset if(reset = ‘1’) then a_out <= x”00”; data_out <= x”00”; else if (sel = ‘1’) then a_out <= a; data_out <= my_data; end if; end if; end if; end process; process (sel, a, my_data) begin -- default all driven signals a_out <= x”00”; data_out <= x”00”; if (sel = ‘1’) then a_out <= a; data_out <= my_data; end if; end process;
State Machine Structure -- Compute next state process (STATE, x) begin -- defaults next_state <= STATE; case STATE is when S1 => if(x = ‘0’) then Next_STATE <= S1; else Next_STATE <= S2; end if; when S2 => Next_State <= S1; end if; end process; -- Assign STATE to next state process (clk) begin -- check for rising edge of the clk if(clk’event and clk = ‘1’) then -- initialize all driven signals during reset if(reset = ‘1’) then STATE <= S1; else STATE <= Next_STATE; end if; end if; end process; No memory!!!! Has memory (e.g. flip-flops)
Manage Registers/Counters -- Manage Registers/Counters process (clk) begin if(clk’event and clk = ‘1’) then -- initialize all driven signals during reset if(reset = ‘1’) then store_x_reg <= x”00”; counter_1 <= x“00”; else -- update registers and counters if(update_reg) then store_x_reg <= new_val; end if; if(update_count) then counter_1 <= new_count; end if; end if; end if; end process; These are memory elements (e.g. flip-flops)
Good papers on state machine design • FSM “good practices” paper (Note: inVerilog) • http://www.sunburst-design.com/papers/ • The Fundamentals of Efficient Synthesizable Finite State Machine (2002) • Synthesizable Finite State Machine Design Techniques(2003)
Common Mistakes in more detail • See Common VHDL mistakes pdf on course web
Common Mistakes in more detail Correct Example of a counter
Next Class • Short History of Reconfigurable computing and applicaitons
