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CS4100: 計算機結構 Pipelining

CS4100: 計算機結構 Pipelining. 國立清華大學資訊工程學系 一零零 學年度第二學期. Outline. An overview of pipelining A pipelined datapath Pipelined control Data hazards and forwarding Data hazards and stalls Branch hazards Exceptions Superscalar and dynamic pipelining. A. B. C. D. Pipelining Is Natural!.

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CS4100: 計算機結構 Pipelining

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  1. CS4100: 計算機結構Pipelining 國立清華大學資訊工程學系 一零零學年度第二學期

  2. Outline • An overview of pipelining • A pipelined datapath • Pipelined control • Data hazards and forwarding • Data hazards and stalls • Branch hazards • Exceptions • Superscalar and dynamic pipelining Pipelining-1

  3. A B C D Pipelining Is Natural! • Laundry example: Ann, Brian, Cathy, Dave each have one load ofclothes to wash, dry,and fold Washer takes 30 minutes Dryer takes 40 minutes “Folder” takes 20 minutes Pipelining-2

  4. A B C D Sequential Laundry 6 PM Midnight 7 8 9 11 10 • Sequential laundry takes 6 hours for 4 loads • If they learned pipelining, how long would it take? Time 30 40 20 30 40 20 30 40 20 30 40 20 T a s k O r d e r Pipelining-3

  5. 30 40 40 40 40 20 A B C D Pipelined Laundry: Start ASAP 6 PM Midnight 7 8 9 11 10 • Pipelined laundry takes 3.5 hours for 4 loads Time T a s k O r d e r Pipelining-4

  6. 30 40 40 40 40 20 A B C D Pipelining Lessons 6 PM 7 8 9 • Doesn’t help latency of single task, but throughput of entire • Pipeline rate limited by slowest stage • Multiple tasks working at same time using different resources • Potential speedup = Number pipe stages • Unbalanced stage length; time to “fill” & “drain” the pipeline reduce speedup • Stall for dependences Time T a s k O r d e r Pipelining-5

  7. Ifetch Reg Exec Mem Wr Store Ifetch Reg Exec Mem Wr R-type Ifetch Reg Exec Mem Wr Single cycle vs. Pipeline Cycle 1 Cycle 2 Clk Single Cycle Implementation: Load Store Waste Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Clk Pipeline Implementation: Load Pipelining-6

  8. Pipeline Performance Single-cycle (Tc= 800ps) Pipelined (Tc= 200ps) Pipelining-7

  9. Im Dm Reg Reg ALU Im Dm Reg Reg ALU Im Dm Reg Reg ALU Im Dm Reg Reg ALU Im Dm Reg Reg ALU Why Pipeline? Because the Resources Are There! Time (clock cycles) Single-cycle Datapath Inst 0 I n s t r. O r d e r Inst 1 Inst 2 Inst 3 Inst 4 Pipelining-8

  10. Outline • An overview of pipelining • A pipelined datapath • Pipelined control • Data hazards and forwarding • Data hazards and stalls • Branch hazards • Exceptions • Superscalar and dynamic pipelining Pipelining-9

  11. Designing a Pipelined Processor • Examine the datapath and control diagram • Starting with single cycle datapath • Single cycle control? • Partition datapath into stages: • IF (instruction fetch), ID (instruction decode and register file read), EX (execution or address calculation), MEM (data memory access), WB (write back) • Associate resources with stages • Ensure that flows do not conflict, or figure out how to resolve • Assert control in appropriate stage Pipelining-10

  12. Multi-Execution Steps But, use single-cycle datapath ... Pipelining-11

  13. Feedback Path Split Single-cycle Datapath What to add to split the datapath into stages? Pipelining-12

  14. Add Pipeline Registers • Use registers between stages to carry data and control Pipeline registers (latches) Pipelining-13

  15. Ifetch Reg/Dec Exec Mem Wr Consider load • IF: Instruction Fetch • Fetch the instruction from the Instruction Memory • ID: Instruction Decode • Registers fetch and instruction decode • EX: Calculate the memory address • MEM: Read the data from the Data Memory • WB: Write the data back to the register file Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Load Pipelining-14

  16. 1st lw Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Pipelining load • 5 functional units in the pipeline datapath are: • Instruction Memory for the Ifetch stage • Register File’s Read ports (busA and busB) for the Reg/Dec stage • ALU for the Exec stage • Data Memory for the MEM stage • Register File’s Write port (busW) for the WB stage Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Clock 2nd lw 3rd lw Pipelining-15

  17. IF Stage of load • IR = mem[PC]; PC = PC + 4 IR, PC+4 Pipelining-16

  18. ID Stage of load • A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; Pipelining-17

  19. EX Stage of load • ALUout = A + sign-ext(IR[15-0]) Pipelining-18

  20. MEM State of load • MDR = mem[ALUout] Pipelining-19

  21. WB Stage of load • Reg[IR[20-16]] = MDR Who will supply this address? Pipelining-20

  22. Ifetch Reg/Dec Exec Wr The Four Stages of R-type • IF: fetch the instruction from the Instruction Memory • ID: registers fetch and instruction decode • EX: ALU operates on the two register operands • WB: write ALU output back to the register file Cycle 1 Cycle 2 Cycle 3 Cycle 4 R-type Pipelining-21

  23. Ops! We have a problem! Ifetch Reg/Dec Exec Wr Ifetch Reg/Dec Exec Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Wr Ifetch Reg/Dec Exec Wr Pipelining R-type and load • We have a structural hazard: • Two instructions try to write to the register file at the same time! • Only one write port Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Clock R-type R-type Load R-type R-type Pipelining-22

  24. 1 2 3 4 5 Load Ifetch Reg/Dec Exec Mem Wr 1 2 3 4 R-type Ifetch Reg/Dec Exec Wr Important Observation • Each functional unit can only be used once per instruction • Each functional unit must be used at the same stage for all instructions: • Load uses Register File’s write port during its 5th stage • R-type uses Register File’s write port during its 4th stage Several ways to solve: forwarding, adding pipeline bubble, making instructions same length Pipelining-23

  25. Ifetch Reg/Dec Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Ifetch Reg/Dec Exec Mem Wr Solution: Delay R-type’s Write • Delay R-type’s register write by one cycle: • R-type also use Reg File’s write port at Stage 5 • MEM is a NOP stage: nothing is being done. 4 1 2 3 5 Exec Mem R-type Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Clock R-type R-type Load R-type also has 5 stages R-type R-type Pipelining-24

  26. Ifetch Reg/Dec Exec Mem The Four Stages of store • IF: fetch the instruction from the Instruction Memory • ID: registers fetch and instruction decode • EX: calculate the memory address • MEM: write the data into the Data Memory Add an extra stage: • WB: NOP Cycle 1 Cycle 2 Cycle 3 Cycle 4 Store Wr Pipelining-25

  27. Ifetch Reg/Dec Exec The Three Stages of beq • IF: fetch the instruction from the Instruction Memory • ID: registers fetch and instruction decode • EX: • compares the two register operand • select correct branch target address • latch into PC Add two extra stages: • MEM: NOP • WB: NOP Cycle 1 Cycle 2 Cycle 3 Cycle 4 Beq Mem Wr Pipelining-26

  28. Pipelined Datapath Pipelining-27

  29. Graphically Representing Pipelines • Can help with answering questions like: • How many cycles to execute this code? • What is the ALU doing during cycle 4? • Help understand datapaths Pipelining-28

  30. Example 1: Cycle 1 Pipelining-29

  31. Example 1: Cycle 2 Pipelining-30

  32. Example 1: Cycle 3 Pipelining-31

  33. Example 1: Cycle 4 Pipelining-32

  34. Example 1: Cycle 5 Pipelining-33

  35. Example 1: Cycle 6 Pipelining-34

  36. Outline • An overview of pipelining • A pipelined datapath • Pipelined control • Data hazards and forwarding • Data hazards and stalls • Branch hazards • Exceptions • Superscalar and dynamic pipelining Pipelining-35

  37. Pipeline Control: Control Signals Pipelining-36

  38. Group Signals According to Stages • Can use control signals of single-cycle CPU Fig. 4.22 Pipelining-37

  39. Data Stationary Control • Pass control signals along just like the data • Main control generates control signals during ID Fig. 4.50 Pipelining-38

  40. Data Stationary Control (cont.) • Signals for EX (ExtOp, ALUSrc, ...) are used 1 cycle later • Signals for MEM (MemWr, Branch) are used 2 cycles later • Signals for WB (MemtoReg, MemWr) are used 3 cycles later ID EX MEM WB ExtOp ExtOp ALUSrc ALUSrc ALUOp ALUOp Main Control RegDst RegDst Ex/MEM Register MEM/WB Register ID/Ex Register IF/ID Register MemWr MemWr MemW Branch Branch Branch MemtoReg MemtoReg MemtoReg MemtoReg RegWr RegWr RegWr RegWr Pipelining-39

  41. WB Stage of load • Reg[IR[20-16]] = MDR Who will supply this address? Pipelining-40

  42. Datapath with Control Pipelining-41

  43. Let’s Try it Out lw $10, 20($1) sub $11, $2, $3 and $12, $4, $5 or $13, $6, $7 add $14, $8, $9 Pipelining-42

  44. Example 2: Cycle 1 Pipelining-43

  45. Example 2: Cycle 2 Pipelining-44

  46. Example 2: Cycle 3 Pipelining-45

  47. Example 2: Cycle 4 Pipelining-46

  48. Example 2: Cycle 5 Pipelining-47

  49. Example 2: Cycle 6 Pipelining-48

  50. Example 2: Cycle 7 Fig. 6.34 Pipelining-49

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