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P R O J E C T

P R O J E C T. VLSI 설계 자동화 담당교수님 : 조 준동 교수님. 1. PROJECT : < 4 bit carry lookahead adder 를 이용한 16 bit group ripple carry adder 설계 > < 8 bit braun array multiplier 설계 >

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P R O J E C T

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  1. P R O J E C T VLSI 설계 자동화 담당교수님 : 조 준동 교수님

  2. 1. PROJECT : < 4 bit carry lookahead adder 를 이용한 16 bit group ripple carry adder 설계 > < 8 bit braun array multiplier 설계 > 2. NAME : SKKU 전자공학과 4학년 9251081 박 성민 3. PROJECT GOAL  SCHEMETIC 방식의 설계와 VHDL 방식의 설계 방법을 통해 전반적인 설계 기법을 익히고자 한다.  위 주제의 ADDER 를 설계하고 일반적인 RIPPLE ADDER와 비교 분석을 하고 여러종류의 ADDER 알고리즘을 이해한다.  ADDER 설계가 끝나면 8 BIT BRAUN ARRY MULTIPLIER 를 설계해보고자 한다.

  3. 4. REARCH BACKGROUND 효율적인 회로는 아니지만 위 주제의 설계를 통해서 설계 기법을 기초부터 익히는데 가장 접근하기 쉬운 주제라고 생각해서 선택하였다. 5. Theory 및 design 과정  기본적인 이론과 설계 알고리즘을 세운다.  < SCHEMETIC 설계 방식 , VHDL 설계 방식 > * 4 bit carry lookahead adder >> * 16 bit group ripple carry adder >> * SIMULATION 검증 및 TIME ANALIZING >> * 16 bit ripple carry adder 와 비교, 분석  8 bit braun array multiplier 설계

  4. ADDER 설계 SCHEMATIC V H D L 4bit carry lookahead adder Behavior modeling Behavior modeling 4bit CLA 구성 16bit ripple carry adder symbolize Structure modeling 16bit ripple carry adder 16bit group ripple carry adder 4bit CLA >> 16bit GRCA Simulation time analyze Simulation time analyze Simulation time analyze Simulation time analyze 비교, 분석 비교, 분석

  5. < Theory >  우선 adder 설계를 위한 이론적인 진리표와 논리식을 세운다.  * full adder 진리표

  6. 논리식은 Pi = Ai + Bi = Ai xor Bi(propagation 의미상)

  7. C3 C2 C1 C0 A= A3 A2 A1 A0 B= B3 B2 B1 B0 S3 S2 S1 S0 C4 C3 C2 C1

  8. Ai XOR HSi XOR Si Bi Ci 캐리 예측 논리 Ai-1 Bi-1 Co CARRY LOOKAHEAD ADDER 회로도

  9. 이상으로 기본적인 carry lookahead 이론을 살표보았다. 이 후로 이론을 바탕으로 실제 설계를 시작한다.

  10. SCHEMETIC 설계  4 bit carry lookahead adder >> symbolize >> 16 bit group ripple carry adder >> simulation , time analize 16 bit ripple carry adder >> simulation, time analize 비교, 분석

  11. 4 bit carry lookahead adder

  12. 16 bit group ripple carry adder

  13. 비교 graph

  14. 16 bit ripple carry adder

  15. 비교 graph

  16. 비교 및 분석 Simulation 검증과 time 분석결과 group RCA 가 RCA 보다 speed가 두배정도 빨라지고 waveform에서 보면 glitch가 줄어듬을 볼수 있다.

  17.  V H D L설계  4 bit carry lookahead adder ( behavior modeling ) >> component >> 16 bit group ripple carry adder ( structure modeling ) >> simulation , time analize 16 bit ripple carry adder ( behavior modeling ) >> simulation, time analize 비교, 분석

  18. -- 4 bit carry lookahead adder library ieee; use ieee.std_logic_1164.all; entity cl_4ad is port ( a,b : in std_logic_vector(3 downto 0); c_in : in std_logic; sum : out std_logic_vector(3 downto 0); c_out : out std_logic); end cl_4ad; architecture behavior_description of cl_4ad is signal Ci : std_logic_vector (4 downto 0); begin process (a,b,c_in) variable Gi,Pi : std_logic_vector (3 downto 0); begin Gi := a(3 downto 0) and b(3 downto 0); Pi := a(3 downto 0) or b(3 downto 0); Ci(0) <= c_in; Ci(1) <= Gi(0) or (Pi(0) and Ci(0)); Ci(2) <= Gi(1) or (Pi(1) and Ci(1)); Ci(3) <= Gi(2) or (Pi(2) and Ci(2)); Ci(4) <= Gi(3) or (Pi(3) and Ci(3)); sum(3 downto 0) <= a(3 downto 0) xor b(3 downto 0) xor Ci(3 downto 0); c_out <= Ci(4); end process; end behavior_description; configuration cfg_cl_4ad of cl_4ad is for behavior_description end for; end cfg_cl_4ad; 4 bit carry lookahead adder

  19. -- 16 bit group ripple carry adder library ieee; use ieee.std_logic_1164.all; entity rcl_16ad is port ( a,b : in std_logic_vector(15 downto 0); c_in : in std_logic; sum : out std_logic_vector(15 downto 0); c_out : out std_logic); end rcl_16ad; architecture structure of rcl_16ad is signal C_1,C_2,C_3 : std_logic; component cl_4ad port ( a,b : in std_logic_vector(3 downto 0); c_in : in std_logic; sum : out std_logic_vector(3 downto 0); c_out : out std_logic); end component; begin cl_0:cl_4ad port map (a(3 downto 0),b(3 downto 0),c_in,sum(3 downto 0),C_1); cl_1:cl_4ad port map (a(7 downto 4),b(7 downto 4),C_1,sum(7 downto 4),C_2); cl_2:cl_4ad port map (a(11 downto 8),b(11 downto 8),C_2,sum(11 downto 8),C_3); cl_3:cl_4ad port map (a(15 downto 12),b(15 downto 12),C_3,sum(15 downto 12),c_out); end structure; 16 bit group ripple carry adder

  20. 비교 graph

  21. 16 bit ripple carry adder -- 2 bit full adder library ieee; use ieee.std_logic_1164.all; entity fuad is port ( x,y : in std_logic; c_in : in std_logic; s_out,c_out : out std_logic); end fuad; architecture structure of fuad is begin process begin c_out <= (x and y) or (c_in and (x or y)); s_out <= x xor y xor c_in; end process; end structure; configuration cfg_fuad of fuad is for structure end for; end cfg_fuad; -- 16 bit ripple carry adder library ieee; use ieee.std_logic_1164.all; entity rcad is port ( a,b : in std_logic_vector(15 downto 0); c_in : in std_logic; sum : out std_logic_vector(15 downto 0); c_out : out std_logic); end rcad; architecture structure of rcad is signal C_1,C_2,C_3,C_4,C_5,C_6,C_7,C_8,C_9,C_10,C_11,C_12, C_13,C_14,C_15 : std_logic; component fuad port ( x,y : in std_logic; c_in : in std_logic; s_out : out std_logic; c_out : out std_logic); end component; 뒷면 계속

  22. begin cl_0:fuad port map (a(0),b(0),c_in,sum(0),C_1); cl_1:fuad port map (a(1),b(1),C_1,sum(1),C_2); cl_2:fuad port map (a(2),b(2),C_2,sum(2),C_3); cl_3:fuad port map (a(3),b(3),C_3,sum(3),C_4); cl_4:fuad port map (a(4),b(4),C_4,sum(4),C_5); cl_5:fuad port map (a(5),b(5),C_5,sum(5),C_6); cl_6:fuad port map (a(6),b(6),C_6,sum(6),C_7); cl_7:fuad port map (a(7),b(7),C_7,sum(7),C_8); cl_8:fuad port map (a(8),b(8),C_8,sum(8),C_9); cl_9:fuad port map (a(9),b(9),C_9,sum(9),C_10); cl_10:fuad port map (a(10),b(10),C_10,sum(10),C_11); cl_11:fuad port map (a(11),b(11),C_11,sum(11),C_12); cl_12:fuad port map (a(12),b(12),C_12,sum(12),C_13); cl_13:fuad port map (a(13),b(13),C_13,sum(13),C_14); cl_14:fuad port map (a(14),b(14),C_14,sum(14),C_15); cl_15:fuad port map (a(15),b(15),C_15,sum(15),c_out); end structure;

  23. 비교 graph

  24. 비교 및 분석 VHDL 설계에서는 Simulation 검증과 time 분석결과 group RCA 와 RCA 가 speed가 거의 똑같았고 waveform에서 보면 glitch가 줄어듬을 볼수 있다.

  25. 전체 비교 및 분석 V(Vhdl), S(Schemetic)

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