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1. Ｅｘｅｒｃｉｓｅ TAIST ICTES Program VLSI Design Methodology Hiroaki Kunieda Tokyo Institute of Technology

2. 1. Fabrication process such as CMOS process must be decided in prior to design. Describe the reason why ? 2. The substrate of nMOS transistor must be connected to ground, while the substrate of pMOS transistor must be connected to VDD, power supply. Describe the reason why ? 3. What decide the maximum LSI speed or clock frequency ? 4. Describe the difference between Digital LSI and Analog LSI. 5. What is the reason why LSI manufacturing requires volume production ? 6. Why LSI costs are decided by chip area ? 7. Why LSI reliability is much more than the discrete circuits ? 8. Why place and rout affects the performance of LSI ? 9. CMOS process is preferred to NMOS process or Bipolar process. Describe the reason. 10. What is the role of the stray or parasitic capacitance ? 1.VLSI Overview

3. [1] The nMOS pull down logic gates blocks are shown in the figure. Draw the complete CMOS circuit. Derive the logic function. Draw the stick diagram layout of the CMOS circuit. Draw the complete pseudo-NMOS circuit by adding a pMOS transistor. Draw the complete CMOS domino logic to achieve the same logic function. Derive the channel width and length of CMOS gate, which has the same characteristics in terms of rise and fall times as a CMOS inverter consisting of nMOS of W/L=250/25 and pMOS of W/L = 400/25. 2.VLSI Basic 1

4. [2] Figure shows Gate Array layout mask patterns, which consists of basic cells. Basic cell is a identical transistor cell. Gate Array employs only metal and its contact window masks over the pre-manufactured • Transistor array. • Describe basic cell. • Derive the circuit of the figure. • Show the width and length of transistor used in the figure. • Describe functional behavior of the circuit. • This circuit is used as shown in figure. Describe the function of this circuit. 2.VLSI Basic 2

5. 2.VLSI Basic 2

6. Gate Delay CMOS Driver sends signal through wireto 10 CMOS Gates. Calculate gate delay of the driver without and with wire delays. CMOS Inverter has On Resistance Ro/W and output and input capacitor CoW for channel width of W/25nm, where Ro is 200 Ωum, Co=50fF/um. VDD=1.0V, VT=0.4V Wire unit resistance is Rline=500Ω/mm、wire unit capacitor is Cline=300fF/mm.

7. wire Delay

8. Standard Cell Design has many advantages over another design. 1. Layout design can automatically be performed by CAD tool. Describe the reason. 2. Logic Synthesis can also be performed with excellent design compiler. In order to run logic synthesizer, what data of standard cells are needed ? 3. What is a major requirement for each standard cell ? On the other hand, standard cell design is not optimal solution, in terms of design optimization. 1. Describe the reason why the designed schematic circuits are not optimal in terms of power, speed, and chip area. 2. Gate Array is a semi custom design so that wefa can be fabricated in prior to design requirement. Describe the reason why standard cell is not semi custom design in the same sense as Gate Array. 3.Standard Cell Overview

9. Describe both data path and control circuit of Figure by VerilogHDL. After the starting signal S raises, the circuit of Figure accepts a sequence of input data and accumulates them. 4. Verilog HDL

10. 5. Logic Design • Consider logic function • F=ab’cd+ab’e+b’d’e+f • Find out kernel and its cofactor of the logic function. • Show the algebraic division by selecting one of kernels. • Repeat until no further division is made.

11. 5. Logic Design [1] Consider to design Standard Cell LSI for Figure 1. While, Table 1 shows the specification or the truth table of combinatorial circuit Fc, which is a subsystem of the state machine Sm as shown in Figure 1. Describe the state transition graph of the state machine Sm. Describe 4 outputs of the combinatorial circuit Fc by logic equations. Derive kernels and their cofactors of each logic function of the combinatorial circuit Fc. Do logic synthesis for the combinatorial circuit Fc and draw the logic circuit. Suppose that we have only cells such as 3 input NAND, AND-OR-Inverters and so on in standard cell library. Please perform technology mapping for the logic circuit of the combinatorial circuit Fc.

12. Describe VerilogHDL for this state machine Sm. Suppose that we do simulation of the state machine in order to verify correctness of your VerilogHDL, Draw the timing chart of the machine Sm. Assume that clock frequency is 100MHz and gate delay of each cell is 3 nsec and FF works with no delay. By deriving Binary Decision Diagram (BDD), perform formal verification for the derived logic circuit of the combinatorial circuit Fc as follows. 5.1) Derive BDD from the truth table 1. 5.2) Derive BDD for 3input-NAND and AOI(AND-OR Inverter) from the derive circuit of the combinatorial circuit Fc. Describe scan path design for the state machine of Figure 1 and describe how to test the state machine with scan path. Describe why this scan path design is necessary.

13. 6. Logic Verification Perform formal verification of the above logic circuit using BDD Representation.

14. Sum Generation Function

15. Carry Generation Function

16. Carry Generation Function

17. 7. Placement • 2] Suppose that the derived circuit is shown as in Figure 2. • Decide the placement of all gates in one row for the circuit by using the model of standard cells as shown in Fig.3. • Do the interconnection between those gates. The number of horizontal tracks used in channel routing should be minimized. • Describe the reason why, after layout, we should perform again timing analysis. • Suppose that all gate delays are 1nsec and all wire delays are 1nsec. Calculate the total delays on critical path.

18. 7. Layout Design Suppose that above graph represents connections between different Standard cells placed in a row. Find out the best placement of this Standard cells.

19. 7. Layout Design 10 1 7 13 5 10 3 9 6 4 3 8 11 12 0 8 5 5 7 0 1 3 11 2 9 4 11 8 13 12 6 2 • Above figure shows routing channel with net number to be connected. • Net 0 indicates no connection. • Try routing by left edge method. • Draw a restriction graph, whose node corresponds to net, and • whose edge corresponds to the relationship of overlapping of area.

20. Module Test(clock, X); Input clock, X; output Y; reg [1:0] current_state, next_state; parameter s0=2’b00, s1=2’b01, s2=2’b11, s3=2’b10; always @(posedge clock) current_state<=next_state; always @(current_state or input) begin case(current_state) s0: next_state<=X?s1:s0; s1: next_state<=s2; s2: next_state<=s3; s3: next_state<=s0; default:next_state<=s0; endcase end always @(current_state or X) begin case(current_state) s0: Y <=0; s1: Y <=0; s2: Y <=0; s3: Y <=1; default:output<=0; endcase end endmodule Describe the state transition diagram Obtain the state transition table with input (Q1, Q0, X) and output (D1, D0, Y), where (Q1, Q0) are corresponding to states s0-s3 and (D1, D0) are inputs of FFs for (Q1, Q0) respectively. Obtain the logic functions D1, D0, and Y, respectively. Describe the state machine by using the combinational logic block with input (Q1, Q0, X) and output (D1, D0, Y).

22. [4] 2 D-FFs, OR-AND and AND standard cells are shown in Figure 2 with interconnection information. Verify the net number on the terminal of 2 D-FFs and OR-AND and AND cells by showing the routing between those cells in an upper channel routing area. Suppose that the input comes from the left side and the out goes out to the right side in the routing channel. Place them in 1 dimensional row so as to minimize the number of tracks in routing channel. Please explain what is the clock tree insertion and explain the reason why clock tree insertion should be conducted in between placement and routing procedure. Show the optimal routing in an upper channel area to realize the state machine.