Improving noc based testing through compression schemes
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1. 2. Improving NoC-based Testing Through Compression Schemes. Érika Cota 1 Julien Dalmasso 2 Marie-Lise Flottes 2 Bruno Rouzeyre 2 WNOC 2007. Introduction. SoC design communication among cores Network-on-chip. SoC testing access to cores

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Improving NoC-based Testing Through Compression Schemes

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Improving noc based testing through compression schemes

1

2

Improving NoC-based Testing Through Compression Schemes

Érika Cota1 Julien Dalmasso2

Marie-Lise Flottes2 Bruno Rouzeyre2

WNOC 2007


Introduction

Introduction

SoC design

  • communication among cores

  • Network-on-chip

SoC testing

  • access to cores

  • 1500 standard

NoC-based SoC

  • available access to each embedded core

  • efficient communication mechanism

  • reuse the NoC as Test Access Mechanism (TAM)


Noc based system

NoC-based system

Wrapper

SoC

core

core

core

Router

core

core

core


Noc based testing

NoC-based testing

ATE

SoC

core

core

core

core

core

core


Reuse model

Reuse Model

ATE

SoC

core

core

core

core

core

core


Reuse model1

Reuse Model

ATE

SoC

core

core

core

core

core

core


Reuse model2

Reuse Model

Wrapper:

- test mode

- basic 1500 modes

SoC

core

core

core

core

core

core


Noc based testing1

NoC-based Testing

  • Minimize total test time:

    • Maximize the use of network resources during test

  • Test scheduling techniques

    • Preemptive

    • Non-preemptive

  • Wrappers design

    • NoC protocol

    • 1500-compliant


Noc based testing approaches

NoC-based Testing Approaches

  • Preemptive testing

    • One vector per message, non-reserved paths

  • Non-preemptive testing

    • All vectors in one message, dedicated paths

1 0 1 1

packet header

0 1 0 0

0 0 0 1

test header

flit

flit

CUT

1 0 0 1 1 01

flit

tail


Noc based testing approaches1

NoC-based Testing Approaches

  • Preemptive testing

    • One vector per message, non-reserved paths

  • Non-preemptive testing

    • All vectors in one message, dedicated paths

    • More than 1 scan slice per flit

1 0 11

packet header

0 1 00

0 0 01

test header

Slice 1

Slice 2

flit

CUT

1 0 011 01

flit

tail


Noc based testing approaches2

NoC-based Testing Approaches

  • Preemptive testing

    • One vector per message, non-reserved paths

  • Non-preemptive testing

    • All vectors in one message, dedicated paths

    • More than 1 scan slice per flit

1 0 11

packet header

0 1 00

0 0 01

test header

Slice 1

Slice 2

flit

CUT

1 0 011 01

flit

tail


Reuse model number of test ports

Reuse Model: number of Test Ports

ATE = 2W channels

SoC

core

core

core

w

w

w

w

w

core

core

core

  • 1 core under test


Reuse model number of test ports1

Reuse Model: number of Test Ports

ATE = 4W channels

SoC

w

w

w

w

core

core

core

w

w

w

w

w

core

core

core

  • 2 cores under test


Dft costs

Test Time

Number of Extra Pins

DfT Costs

  • p93791

  • 103 Inputs

  • 79 Outputs

  • 66 Bidirs

  • 32 Cores


Ate costs

Test Time

Number of ATE Channels

ATE Costs

  • p93791

  • 103 Inputs

  • 79 Outputs

  • 66 Bidirs

  • 32 Cores


Problem

Problem

How to increase the number of test ports

Increase test parallelism

Maximize NoC channels usage

without increasing the ATE cost?


Improving noc based testing through compression schemes

Goal

Goal:

  • Use Horizontal compression to reduce the number of ATE channels required for each NoC test port, i.e. to increase the number of test ports

    How ?

  • Combine a horizontal compression scheme with a non–preemptive test scheduling approach to reduce test time


Improving noc based testing through compression schemes

Outline

  • Compression applied to NoC-based testing

  • Horizontal compression method

  • Test scheduling algorithm

  • Experimental results

  • Final remarks


Compression applied to noc based test

Core

Core

router

router

router

router

wrapper

wrapper

W

W

Core

Core

N

W

wrapper

wrapper

W

W

Compression Applied to NoC-based Test

W

input


Compression applied to noc based test1

router

Compression Applied to NoC-based Test

Functional

input pins

NoC

Fi

Core i

M

decompressor

wrapper

W

W

W

Communication

channels

W

M≤ Fi ≤ W


Compression applied to noc based test2

router

Compression Applied to NoC-based Test

Functional

output pins

NoC

Fi

Core i

M

compressor

wrapper

W

W

W

Communication

channels

W

M≤ Fi ≤ W


Compression applied to noc based test3

router

Compression Applied to NoC-based Test

  • Each test port needs less than W bits

  • Less ATE channels per port

  • Increase the number of possible test ports

  • Increase test parallelism

Functional

input pins

NoC

Fi

Core i

Wk

decompressor

wrapper

W

W

W

Communication

channels

W

Wk≤ Fi ≤ W


Compression applied to noc based test4

Compression Applied to NoC-based Test

  • Horizontal compression

    • Test width reduction is the primary goal

  • Test vectors compression

    • Implies extra hardware at NoC-level (decompressor sharing)

    • May increase cores test time

  • Test responses compression

    • Implies extra hardware at NoC-level

    • Does not affect core test time


Horizontal compression techniques

On-chip Decompressor

Compression

W Scan Chains

Compressed

Test Data

Test Data

W

W

Core

M

M

ATE

Outline

Horizontal Compression Techniques

  • Compression applied to NoC-based testing

  • Horizontal compression method

  • Test scheduling algorithm

  • Experimental results

  • Final remarks

M < W


Horizontal compression requirements

Horizontal Compression: Requirements

  • Features

    • Circuit netlist independent (suitable for IPs)

    • Test data independent (additional test patterns)

    • Specific tools independent

    • Low cost hardware decompressor

  • No impact on fault coverage

  • Allow Shared decompressor for several cores


Horizontal compression

Horizontal Compression

  • Many published methods

  • Take advantage of Don’t Care bits (X’s) in test sequence

  • May increase core Test Time


Decompressor architecture

Decompressor architecture

From ATE

M

0

0

0

0

Add Cells

Output

Shift Register

W

To scan chains

[1] Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre: Fitting ATE Channels with Scan Chains: a Comparison between a Test Data Compression Technique and Serial Loading of Scan Chains - DELTA 2006: 295-300


Decompression synchronization

0

0

1

0

1

1

1

1

0

0

1

0

1

1

1

1

1

1

1

1

1

1

0

0

X

1

1

1

0

1

1

0

1

0

1

0

0

0

1

0

1

X

0

0

1

0

0

1

1

X

X

1

1

1

1

0

1

X

0

X

0

X

X

1

0

1

0

0

X

0

X

1

X

1

X

X

1

1

0

X

X

0

0

X

X

0

0

0

X

X

X

1

0

X

X

1

X

1

X

1

X

X

X

X

X

0

X

0

X

0

X

X

X

0

X

0

X

X

X

0

Decompression synchronization

Original test Sequence

Scan enable

Control

0

0

S1 -> S2 : 0 1

S2 -> S3 : 1 1

S3 -> S4 : - -

Compressed test Sequence

Sc11 0

Sc20 0

FSM

Sc30 1

Sc41 1

CLK

Sc50 1

Sc61 0


Compression applied to noc data

Compression Applied to NoC Data

Test pattern: 011010110101110

Compressed test packet

(M = 2)

Original test packet

(W= 5)

Uncompressed test packet

(W = 5)

packet header

packet header

packet header

packet header

test header

test header

packet header

01101

01101

test header

01101

01101

test header

01110

01110

test header

tail

tail

01

10

compressor

decompressor

1X

00

01

tail


Compression applied to noc based test5

Compression Applied to NoC-based Test

  • Example for d695 ITC’02 benchmark

    • uncompressed and compressed data (#flits)

Compression may increase test time of individual cores


Compression applied to noc based test6

32 ATE

channels

Compression Applied to NoC-based Test

  • Conclusion:

  • Local increase in test time

  • Increase test parallelism

  • Global test time reduction

  • d695

  • 32 Inputs

  • 32 Outputs

  • 10 Cores

33%


Improving noc based testing through compression schemes

Outline

  • Compression applied to NoC-based testing

  • Horizontal compression method

  • Test scheduling algorithm

  • Experimental results

  • Final remarks


Test scheduling using dedicated paths

Test Scheduling Using Dedicated Paths

  • Each core is associated with a routing path

    • Includes input and output ports

  • All resources are reserved until test completed

  • Test pipeline maintained

  • No complex logic

  • Similar to a circuit switching

  • Efficiently assign I/Os and paths to core

    • Each input port leads to a different core test time

[2] C. Liu, E. Cota, H. Sharif, D.K. Pradhan: Test Scheduling for Network-on-Chip with BIST and Precedence Constraints - ITC2004: pp. 1369-1378.


Test scheduling with compression

Test Scheduling with Compression

  • Two test packets per core

    • Compressed test vectors

    • Uncompressed test responses

  • Pre-defined number of test interfaces

    • Number of inputs = number of outputs

    • List of I/O pairs

  • For each core and for each I/O pair

    • Input width changes (compression ratio changes)

    • size of input test packets pre computed


Test scheduling with compression1

Test Scheduling with Compression

Define test

packets

Define access paths

for each core

Select a core

Find available

access path

Schedule

packet


Test scheduling with compression2

Test Scheduling with Compression

Define test

packets

Packets sorted by probable test time

Define access paths

for each core

Select a packet

Find available

access path

Schedule

packet


Test scheduling with compression3

Test Scheduling with Compression

Define test

packets

Packets sorted by probable test time

Define access paths

for each core

Select I/O pair that leads to minimal total test time

Select a packet

Find available

access path

Schedule

packet


Test scheduling with compression4

Test Scheduling with Compression

Define test

packets

Packets sorted by probable test time

Define access paths

for each core

Select I/O pair that leads to minimal total test time

Select a packet

Find available

access path

If no path is found, try next core

Schedule

packet


Test scheduling using dedicated paths1

6

5

4

8

10

7

3

9

2

1

Test Scheduling Using Dedicated Paths

  • d695 from ITC02 benchmark

  • Channel width=32

  • 3 inputs

    • 10, 10, 12bits

  • 3 outputs

  • I/O pairs

    • 3/9

    • 6/7

    • 8/4

1

5

10

2

12

In

10

In

3

6

4

Out

Out

9

8

7

Out

In

10


Test scheduling using dedicated paths2

6

5

4

8

10

7

3

9

2

1

10856

10856

6

6

9869

6

Test Scheduling Using Dedicated Paths

1

5

10

2

12

In

10

In

3

6

4

Out

Out

9

8

7

Out

In

10


Test scheduling using dedicated paths3

5

4

8

10

7

3

9

2

1

15459

6826

6850

5

5

5

9869

6

Test Scheduling Using Dedicated Paths

1

5

10

2

12

In

10

In

3

6

4

Out

Out

9

8

7

Out

In

10


Test scheduling using dedicated paths4

4

8

10

7

3

9

2

1

15115

5829

12655

4

4

4

6826

5

9869

6

Test Scheduling Using Dedicated Paths

1

5

10

2

12

In

10

In

3

6

4

Out

Out

9

8

7

Out

In

10


Test scheduling using dedicated paths5

8

10

7

3

9

2

1

5829

11431

14013

10434

4

8

8

8

6826

5

9869

6

Test Scheduling Using Dedicated Paths

1

5

10

2

12

In

10

In

3

6

4

Out

Out

9

8

7

Out

In

10


Test scheduling using dedicated paths6

10

7

3

9

2

1

5829

10434

4

8

6206

10069

5

10

9869

6

Test Scheduling Using Dedicated Paths

1

5

10

2

12

In

10

In

3

6

4

Out

Out

9

8

7

Out

In

10


Test scheduling using dedicated paths7

7

3

9

2

1

5829

10434

4

8

6206

10069

5

10

9869

13328

7

6

Test Scheduling Using Dedicated Paths

1

5

10

2

12

In

10

In

3

6

4

Out

Out

9

8

7

Out

In

10


Test scheduling using dedicated paths8

3

9

2

1

5829

10434

4

8

6206

10069

12576

5

10

3

9869

13328

7

6

Test Scheduling Using Dedicated Paths

1

5

10

2

12

In

10

In

3

6

4

Out

Out

9

8

7

Out

In

10


Test scheduling using dedicated paths9

9

2

1

5829

10434

11022

4

8

2

6206

10069

12576

5

10

3

9869

13328

7

6

Test Scheduling Using Dedicated Paths

1

5

10

2

12

In

10

In

3

6

4

Out

Out

9

8

7

Out

In

10


Test scheduling using dedicated paths10

9

1

5829

10434

11022

11047

4

8

2

1

6206

10069

12576

5

10

3

9869

13328

7

6

Test Scheduling Using Dedicated Paths

1

5

10

2

12

In

10

In

3

6

4

Out

Out

9

8

7

Out

In

10


Test scheduling using dedicated paths11

9

5829

10434

11022

11047

4

8

2

1

6206

10069

12576

5

10

3

9869

13328

9

7

6

Test Scheduling Using Dedicated Paths

1

5

10

2

12

In

10

In

3

6

4

Out

13412

Out

9

8

7

7

Out

In

10


Test scheduling using dedicated paths12

9

1

5829

10434

11022

11047

4

8

2

1

6206

10069

12576

5

10

3

9869

13328

7

6

Test Scheduling Using Dedicated Paths

1

5

10

2

12

In

10

In

3

6

4

Out

9

Out

9

8

7

Out

In

10


Test scheduling with compression5

Test Scheduling with Compression

Define test

packets

Define access paths

for each core

Select a packet

Permutate cores

Permutate I/O pairs

Find available

access path

Schedule

packet


Experimental setup

Experimental Setup

  • SOCIN Network

    • developed at UFRGS

    • grid topology

    • 32-bit channels

  • ITC’02 SoC Test Benchmarks

    • Cores’ placement from design

    • Random test vectors (80% X's)

  • Test time versus ATE cost


System d695 3 ports example

System D695: 3 ports example


Experimental results d695

Test Time

Number of ATE Channels

Experimental Results – d695

  • d695

  • 32 Inputs

  • 32 Outputs

  • 10 Cores


Experimental results d6951

Test Time

Number of ATE Channels

Experimental Results – d695

  • d695

  • 32 Inputs

  • 32 Outputs

  • 10 Cores


Experimental results d6952

Experimental Results – d695


Experimental results d6953

Experimental Results – d695

- same ATE cost

- 65% test time reduction


Experimental results d6954

Experimental Results – d695

- Test time roughly equivalent

- 50% ATE cost reduction


Experimental results g1023

Experimental Results – g1023


Experimental results g10231

Experimental Results – g1023

  • 38% test time reduction

  • 20% ATE cost reduction


Final remarks

Final Remarks

  • Combination of NoC-based testing and horizontal compression

    • Reduces SoC test time

    • Reduces ATE costs

  • Compression technique

    • compliant with SoC Testing

  • Future works

    • seek for the best partition of ATE channels into test interfaces at NoC-level

    • test time reduction / area overhead trade-off


Improving noc based testing through compression schemes

Thank You…


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