Ece 15b computer organization spring 2010 dmitri strukov
Download
1 / 37

ECE 15B Computer Organization Spring 2010 Dmitri Strukov - PowerPoint PPT Presentation


  • 75 Views
  • Uploaded on

ECE 15B Computer Organization Spring 2010 Dmitri Strukov. Lecture 2: Overview of Computer Organization.

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' ECE 15B Computer Organization Spring 2010 Dmitri Strukov' - ailsa


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
Ece 15b computer organization spring 2010 dmitri strukov

ECE 15B Computer OrganizationSpring 2010Dmitri Strukov

Lecture 2: Overview of Computer Organization

Partially adapted from Computer Organization and Design, 4th edition, Patterson and Hennessy, and classes taught by Patterson at Berkeley, Ryan Kastner at UCSB and Mary Jane Irwin at Penn State


Von neumann computer
“Von-Neumann” Computer

Store –programmed concept

was not invented by John von

Neumann only

Other inventors Presper Eckert

and John Mauchly ENIAC 1943

University of Pensilvania

Keyboard, Mouse

Computer

Processor

Memory

(where

programs,

data

live when

running)

Devices

Disk(where

programs,

data

live when

not running)

Input

Control

Datapath

Output

Display, Printer

ECE 15B Spring 2010


Need many layers to handle complexity

Layers of Abstraction

Need Many Layers to Handle Complexity

This class is about

this region

Application (ex: browser)

Operating

Compiler

System

(Mac OSX)

Software

Assembler

Instruction Set

Architecture

Hardware

Processor

Memory

I/O system

Datapath & Control

Digital Design

Circuit Design

transistors

ECE 15B Spring 2010


Below the program
Below the Program

temp = v[k];

v[k] = v[k+1];

v[k+1] = temp;

lw $t0, 0($2)

lw $t1, 4($2)

sw $t1, 0($2)

sw $t0, 4($2)

High Level Language Program (e.g., C)

Compiler

Assembly Language Program (e.g.,MIPS)

Assembler

0000 1001 1100 0110 1010 1111 0101 1000

1010 1111 0101 1000 0000 1001 1100 0110

1100 0110 1010 1111 0101 1000 0000 1001

0101 1000 0000 1001 1100 0110 1010 1111

Machine Language Program (MIPS)

Machine Interpretation

Hardware Architecture Description (e.g., block diagrams)

Architecture Implementation

Logic Circuit Description(Circuit Schematic Diagrams)


Review unsigned binary representation
Review: Unsigned Binary Representation

231 230 229 . . . 23 22 21 20 bit weight

31 30 29 . . . 3 2 1 0 bit position

1 1 1 . . . 1 1 1 1 bit

1 0 0 0 . . . 0 0 0 0 - 1

232 - 1

232 - 4

232 - 3

232 - 2

232 - 1

ECE 15B Spring 2010


Data input analog digital
Data input: Analog  Digital

  • Real world is analog!

  • To import analog information, we must do two things

    • Sample

      • E.g., for a CD, every 44,100ths of a second, we ask a music signal how loud it is.

    • Quantize

      • For every one of these samples, we figure out where, on a 16-bit (65,536 tic-mark) “yardstick”, it lies.

www.joshuadysart.com/journal/archives/digital_sampling.gif

ECE 15B Spring 2010


Logic design basics
Logic Design Basics

  • Information encoded in binary

    • Low voltage = 0, High voltage = 1

    • One wire per bit

    • Multi-bit data encoded on multi-wire buses

ECE 15B Spring 2010


Grouping of signals
Grouping of signals

ECE 15B Spring 2010


Why binary?

Other logic styles allow for implementations of multilevel logic (e.g. threshold logic)

CMOS digital design style, which is the most power efficient and therefore currently dominating, enforces binary signal representation

ECE 15B Spring 2010


The lowest layer of hierarchy

ECE 15B Spring 2010


How to build combinational elements

A

Y

B

A

A

Mux

I0

Y

+

Y

Y

I1

ALU

B

B

S

F

How to build combinational elements?

  • Adder

    • Y = A + B

  • AND-gate

    • Y = A & B

  • Arithmetic/Logic Unit

    • Y = F(A, B)

  • Multiplexer

    • Y = S ? I1 : I0

ECE 15B Spring 2010




1 bit wide multiplexor
1-bit-wide multiplexor

ECE 15B Spring 2010



4 to 1 multiplexor
4-to-1 multiplexor

ECE 15B Spring 2010


Hierarchical construction of muxes
Hierarchical construction of MUXes

ECE 15B Spring 2010


Building adder
Building adder

ECE 15B Spring 2010


Building adder1
Building adder

ECE 15B Spring 2010


Building adder2
Building adder

ECE 15B Spring 2010


Ripple carry adder
Ripple carry adder

ECE 15B Spring 2010


Circuit delay

ECE 15B Spring 2010


Simple ALU

ECE 15B Spring 2010


Combinational logic
Combinational logic

  • Complex logic blocks are built from basic AND, OR, NOT building blocks we will see shortly

  • A combinational logic block is one in which the output us a function only of its current input

  • Combination logic cannot have memory

ECE 15B Spring 2010


Sequential logic flip flops combination logic
Sequential logic = Flip Flops + combination logic

ECE 15B Spring 2010


How to imple ment
How to implement?

ECE 15B Spring 2010


Will that work
Will that work?

ECE 15B Spring 2010


Sequential elements

D

Q

Clk

Clk

D

Q

Sequential Elements

  • Flip flop: stores data in a circuit

    • Uses a clock signal to determine when to update the stored value

    • Edge-triggered: update when Clk changes from 0 to 1

ECE 15B Spring 2010


Sequential elements1

Clk

D

Q

Write

Write

D

Clk

Q

Sequential Elements

  • Flip flop with write control

    • Only updates on clock edge when write control input is 1

    • Used when stored value is required later

ECE 15B Spring 2010


Register
Register

ECE 15B Spring 2010


D flip flop gate design
D flip flop gate design

ECE 15B Spring 2010



Clock + sequential logic = synchronous design

  • Clock rate (clock cycles per second in MHz or GHz) is inverse of clock cycle time (clock period)

    CC = 1 / CR

one clock period

10 nsec clock cycle => 100 MHz clock rate

5 nsec clock cycle => 200 MHz clock rate

2 nsec clock cycle => 500 MHz clock rate

1 nsec (10-9) clock cycle => 1 GHz (109) clock rate

500 psec clock cycle => 2 GHz clock rate

250 psec clock cycle => 4 GHz clock rate

200 psec clock cycle => 5 GHz clock rate

ECE 15B Spring 2010


Clocking methodology
Clocking Methodology

  • Combinational logic transforms data during clock cycles

    • Between clock edges

    • Input from state elements, output to state element

    • Longest delay determines clock period

ECE 15B Spring 2010


Cpu overview
CPU Overview

ECE 15B Spring 2010


W ith muxes
… with muxes

  • Can’t just join wires together

    • Use multiplexers

ECE 15B Spring 2010


… with muxes

ECE 15B Spring 2010


ad