Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs by Zachary K. Baker and Viktor K. Prasanna University of Southern California, Los Angeles, CA, USA FPL 2004 Review 12-9-04. Presented by Jack Meier. Outline. Introduction Related Work in Automated IDS Generation Approach
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Automatic Synthesis of Efficient IntrusionDetection Systems on FPGAsby Zachary K. Baker and Viktor K. PrasannaUniversity of Southern California, Los Angeles, CA, USAFPL 2004Review 12-9-04
Objective - maximize the number of edges between nodes within the group
& minimize the number of edges between nodes in different groups
Clock Period(has small effect for different #’s ofPartitions)
Area is smallestwith smaller # ofPartitions. (3x range of area)
(Unit Size / Performance * 1000)
Pattern size, average unit size for a 16 character pattern (in logic cells; one slice is two logic cells), and performance (in Mb/s/cell)
(Where are Bloom filters on this chart ?!? )[Whole list of 16-character patterns fit in one filter !]This chart does not consider BlockRAMs!